From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Introduce bindings for TCM memory address space on AMD-xilinx Zynq
UltraScale+ platform. It will help in defining TCM in device-tree
and make it's access platform agnostic and data-driven.
Tightly-coupled memories(TCMs) are low-latency memory that provides
predictable instruction execution and predictable data load/store
timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory
banks on the ATCM and BTCM ports, for a total of 128 KB of memory.
The TCM resources(reg, reg-names and power-domain) are documented for
each TCM in the R5 node. The reg and reg-names are made as required
properties as we don't want to hardcode TCM addresses for future
platforms and for zu+ legacy implementation will ensure that the
old dts w/o reg/reg-names works and stable ABI is maintained.
It also extends the examples for TCM split and lockstep modes.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
---
Changes in v12:
- add "reg", "reg-names" and "power-domains" in pattern properties
- add "reg" and "reg-names" in required list
- keep "power-domains" in required list as it was before the change
Changes in v11:
- Fix yamllint warning and reduce indentation as needed
.../remoteproc/xlnx,zynqmp-r5fss.yaml | 188 ++++++++++++++++--
1 file changed, 168 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
index 78aac69f1060..dc6ce308688f 100644
--- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
@@ -20,9 +20,21 @@ properties:
compatible:
const: xlnx,zynqmp-r5fss
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges:
+ description: |
+ Standard ranges definition providing address translations for
+ local R5F TCM address spaces to bus addresses.
+
xlnx,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
+ default: 1
description: |
The RPU MPCore can operate in split mode (Dual-processor performance), Safety
lock-step mode(Both RPU cores execute the same code in lock-step,
@@ -37,7 +49,7 @@ properties:
2: single cpu mode
patternProperties:
- "^r5f-[a-f0-9]+$":
+ "^r5f@[0-9a-f]+$":
type: object
description: |
The RPU is located in the Low Power Domain of the Processor Subsystem.
@@ -54,8 +66,17 @@ patternProperties:
compatible:
const: xlnx,zynqmp-r5f
+ reg:
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ minItems: 1
+ maxItems: 4
+
power-domains:
- maxItems: 1
+ minItems: 2
+ maxItems: 5
mboxes:
minItems: 1
@@ -101,35 +122,162 @@ patternProperties:
required:
- compatible
+ - reg
+ - reg-names
- power-domains
- unevaluatedProperties: false
-
required:
- compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+allOf:
+ - if:
+ properties:
+ xlnx,cluster-mode:
+ enum:
+ - 1
+ then:
+ patternProperties:
+ "^r5f@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: ATCM internal memory
+ - description: BTCM internal memory
+ - description: extra ATCM memory in lockstep mode
+ - description: extra BTCM memory in lockstep mode
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: atcm0
+ - const: btcm0
+ - const: atcm1
+ - const: btcm1
+
+ else:
+ patternProperties:
+ "^r5f@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: ATCM internal memory
+ - description: BTCM internal memory
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: atcm0
+ - const: btcm0
+
+ power-domains:
+ maxItems: 3
additionalProperties: false
examples:
- |
- remoteproc {
- compatible = "xlnx,zynqmp-r5fss";
- xlnx,cluster-mode = <1>;
-
- r5f-0 {
- compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware 0x7>;
- memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
- mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
- mbox-names = "tx", "rx";
+ #include <dt-bindings/power/xlnx-zynqmp-power.h>
+
+ // Split mode configuration
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ remoteproc@ffe00000 {
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
+ <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
+
+ r5f@0 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>;
+ memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>,
+ <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+ mbox-names = "tx", "rx";
+ };
+
+ r5f@1 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>,
+ <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
+ mbox-names = "tx", "rx";
+ };
};
+ };
+
+ - |
+ //Lockstep configuration
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ remoteproc@ffe00000 {
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
+
+ r5f@0 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x0 0x0 0x0 0x10000>,
+ <0x0 0x20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>,
+ <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+ mbox-names = "tx", "rx";
+ };
- r5f-1 {
- compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware 0x8>;
- memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
- mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
- mbox-names = "tx", "rx";
+ r5f@1 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>,
+ <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
+ mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
+ mbox-names = "tx", "rx";
+ };
};
};
...
--
2.25.1On 01/03/2024 19:16, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > --- > > Changes in v12: > - add "reg", "reg-names" and "power-domains" in pattern properties > - add "reg" and "reg-names" in required list > - keep "power-domains" in required list as it was before the change > > Changes in v11: > - Fix yamllint warning and reduce indentation as needed > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 188 ++++++++++++++++-- > 1 file changed, 168 insertions(+), 20 deletions(-) > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > index 78aac69f1060..dc6ce308688f 100644 > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > @@ -20,9 +20,21 @@ properties: > compatible: > const: xlnx,zynqmp-r5fss > > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: > + description: | > + Standard ranges definition providing address translations for > + local R5F TCM address spaces to bus addresses. > + > xlnx,cluster-mode: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [0, 1, 2] > + default: 1 > description: | > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > lock-step mode(Both RPU cores execute the same code in lock-step, > @@ -37,7 +49,7 @@ properties: > 2: single cpu mode > > patternProperties: > - "^r5f-[a-f0-9]+$": > + "^r5f@[0-9a-f]+$": > type: object > description: | > The RPU is located in the Low Power Domain of the Processor Subsystem. > @@ -54,8 +66,17 @@ patternProperties: > compatible: > const: xlnx,zynqmp-r5f > > + reg: > + minItems: 1 > + maxItems: 4 > + > + reg-names: > + minItems: 1 > + maxItems: 4 > + > power-domains: > - maxItems: 1 > + minItems: 2 > + maxItems: 5 > > mboxes: > minItems: 1 > @@ -101,35 +122,162 @@ patternProperties: > > required: > - compatible > + - reg > + - reg-names > - power-domains > > - unevaluatedProperties: false > - > required: > - compatible > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +allOf: > + - if: > + properties: > + xlnx,cluster-mode: > + enum: > + - 1 > + then: > + patternProperties: > + "^r5f@[0-9a-f]+$": > + type: object > + > + properties: > + reg: > + minItems: 1 > + items: > + - description: ATCM internal memory > + - description: BTCM internal memory > + - description: extra ATCM memory in lockstep mode > + - description: extra BTCM memory in lockstep mode > + > + reg-names: > + minItems: 1 > + items: > + - const: atcm0 > + - const: btcm0 > + - const: atcm1 > + - const: btcm1 Why power domains are flexible? > + > + else: > + patternProperties: > + "^r5f@[0-9a-f]+$": > + type: object > + > + properties: > + reg: > + minItems: 1 > + items: > + - description: ATCM internal memory > + - description: BTCM internal memory > + > + reg-names: > + minItems: 1 > + items: > + - const: atcm0 > + - const: btcm0 > + > + power-domains: > + maxItems: 3 Please list power domains. > > additionalProperties: false Best regards, Krzysztof
On 3/9/24 7:25 AM, Krzysztof Kozlowski wrote: > On 01/03/2024 19:16, Tanmay Shah wrote: > > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > > UltraScale+ platform. It will help in defining TCM in device-tree > > and make it's access platform agnostic and data-driven. > > > > Tightly-coupled memories(TCMs) are low-latency memory that provides > > predictable instruction execution and predictable data load/store > > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > > > The TCM resources(reg, reg-names and power-domain) are documented for > > each TCM in the R5 node. The reg and reg-names are made as required > > properties as we don't want to hardcode TCM addresses for future > > platforms and for zu+ legacy implementation will ensure that the > > old dts w/o reg/reg-names works and stable ABI is maintained. > > > > It also extends the examples for TCM split and lockstep modes. > > > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > > --- > > > > Changes in v12: > > - add "reg", "reg-names" and "power-domains" in pattern properties > > - add "reg" and "reg-names" in required list > > - keep "power-domains" in required list as it was before the change > > > > Changes in v11: > > - Fix yamllint warning and reduce indentation as needed > > > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 188 ++++++++++++++++-- > > 1 file changed, 168 insertions(+), 20 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > index 78aac69f1060..dc6ce308688f 100644 > > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > @@ -20,9 +20,21 @@ properties: > > compatible: > > const: xlnx,zynqmp-r5fss > > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > + ranges: > > + description: | > > + Standard ranges definition providing address translations for > > + local R5F TCM address spaces to bus addresses. > > + > > xlnx,cluster-mode: > > $ref: /schemas/types.yaml#/definitions/uint32 > > enum: [0, 1, 2] > > + default: 1 > > description: | > > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > > lock-step mode(Both RPU cores execute the same code in lock-step, > > @@ -37,7 +49,7 @@ properties: > > 2: single cpu mode > > > > patternProperties: > > - "^r5f-[a-f0-9]+$": > > + "^r5f@[0-9a-f]+$": > > type: object > > description: | > > The RPU is located in the Low Power Domain of the Processor Subsystem. > > @@ -54,8 +66,17 @@ patternProperties: > > compatible: > > const: xlnx,zynqmp-r5f > > > > + reg: > > + minItems: 1 > > + maxItems: 4 > > + > > + reg-names: > > + minItems: 1 > > + maxItems: 4 > > + > > power-domains: > > - maxItems: 1 > > + minItems: 2 > > + maxItems: 5 > > > > mboxes: > > minItems: 1 > > @@ -101,35 +122,162 @@ patternProperties: > > > > required: > > - compatible > > + - reg > > + - reg-names > > - power-domains > > > > - unevaluatedProperties: false > > - > > required: > > - compatible > > + - "#address-cells" > > + - "#size-cells" > > + - ranges > > + > > +allOf: > > + - if: > > + properties: > > + xlnx,cluster-mode: > > + enum: > > + - 1 > > + then: > > + patternProperties: > > + "^r5f@[0-9a-f]+$": > > + type: object > > + > > + properties: > > + reg: > > + minItems: 1 > > + items: > > + - description: ATCM internal memory > > + - description: BTCM internal memory > > + - description: extra ATCM memory in lockstep mode > > + - description: extra BTCM memory in lockstep mode > > + > > + reg-names: > > + minItems: 1 > > + items: > > + - const: atcm0 > > + - const: btcm0 > > + - const: atcm1 > > + - const: btcm1 > > Why power domains are flexible? > > > + > > + else: > > + patternProperties: > > + "^r5f@[0-9a-f]+$": > > + type: object > > + > > + properties: > > + reg: > > + minItems: 1 > > + items: > > + - description: ATCM internal memory > > + - description: BTCM internal memory > > + > > + reg-names: > > + minItems: 1 > > + items: > > + - const: atcm0 > > + - const: btcm0 > > + > > + power-domains: > > + maxItems: 3 > > Please list power domains. Hello, Sent v13 addressing both comments. Thanks. > > > > additionalProperties: false > > > Best regards, > Krzysztof >
On 11/03/2024 19:39, Tanmay Shah wrote: >>> + >>> + else: >>> + patternProperties: >>> + "^r5f@[0-9a-f]+$": >>> + type: object >>> + >>> + properties: >>> + reg: >>> + minItems: 1 >>> + items: >>> + - description: ATCM internal memory >>> + - description: BTCM internal memory >>> + >>> + reg-names: >>> + minItems: 1 >>> + items: >>> + - const: atcm0 >>> + - const: btcm0 >>> + >>> + power-domains: >>> + maxItems: 3 >> >> Please list power domains. > > Hello, > > Sent v13 addressing both comments. > And gave me exactly two hours to disagree? Best regards, Krzysztof
On 3/12/24 7:10 AM, Krzysztof Kozlowski wrote: > On 11/03/2024 19:39, Tanmay Shah wrote: > >>> + > >>> + else: > >>> + patternProperties: > >>> + "^r5f@[0-9a-f]+$": > >>> + type: object > >>> + > >>> + properties: > >>> + reg: > >>> + minItems: 1 > >>> + items: > >>> + - description: ATCM internal memory > >>> + - description: BTCM internal memory > >>> + > >>> + reg-names: > >>> + minItems: 1 > >>> + items: > >>> + - const: atcm0 > >>> + - const: btcm0 > >>> + > >>> + power-domains: > >>> + maxItems: 3 > >> > >> Please list power domains. > > > > Hello, > > > > Sent v13 addressing both comments. > > > > And gave me exactly two hours to disagree? I am sorry, I thought I was addressing the right comments. It was minor change tempted me to push new revision, will wait longer next time. > > Best regards, > Krzysztof >
Hello Krzysztof, Thanks for reviews. Please find my comments below. On 3/9/24 7:25 AM, Krzysztof Kozlowski wrote: > On 01/03/2024 19:16, Tanmay Shah wrote: > > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > > UltraScale+ platform. It will help in defining TCM in device-tree > > and make it's access platform agnostic and data-driven. > > > > Tightly-coupled memories(TCMs) are low-latency memory that provides > > predictable instruction execution and predictable data load/store > > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > > > The TCM resources(reg, reg-names and power-domain) are documented for > > each TCM in the R5 node. The reg and reg-names are made as required > > properties as we don't want to hardcode TCM addresses for future > > platforms and for zu+ legacy implementation will ensure that the > > old dts w/o reg/reg-names works and stable ABI is maintained. > > > > It also extends the examples for TCM split and lockstep modes. > > > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > > --- > > > > Changes in v12: > > - add "reg", "reg-names" and "power-domains" in pattern properties > > - add "reg" and "reg-names" in required list > > - keep "power-domains" in required list as it was before the change > > > > Changes in v11: > > - Fix yamllint warning and reduce indentation as needed > > > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 188 ++++++++++++++++-- > > 1 file changed, 168 insertions(+), 20 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > index 78aac69f1060..dc6ce308688f 100644 > > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > @@ -20,9 +20,21 @@ properties: > > compatible: > > const: xlnx,zynqmp-r5fss > > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > + ranges: > > + description: | > > + Standard ranges definition providing address translations for > > + local R5F TCM address spaces to bus addresses. > > + > > xlnx,cluster-mode: > > $ref: /schemas/types.yaml#/definitions/uint32 > > enum: [0, 1, 2] > > + default: 1 > > description: | > > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > > lock-step mode(Both RPU cores execute the same code in lock-step, > > @@ -37,7 +49,7 @@ properties: > > 2: single cpu mode > > > > patternProperties: > > - "^r5f-[a-f0-9]+$": > > + "^r5f@[0-9a-f]+$": > > type: object > > description: | > > The RPU is located in the Low Power Domain of the Processor Subsystem. > > @@ -54,8 +66,17 @@ patternProperties: > > compatible: > > const: xlnx,zynqmp-r5f > > > > + reg: > > + minItems: 1 > > + maxItems: 4 > > + > > + reg-names: > > + minItems: 1 > > + maxItems: 4 > > + > > power-domains: > > - maxItems: 1 > > + minItems: 2 > > + maxItems: 5 > > > > mboxes: > > minItems: 1 > > @@ -101,35 +122,162 @@ patternProperties: > > > > required: > > - compatible > > + - reg > > + - reg-names > > - power-domains > > > > - unevaluatedProperties: false > > - > > required: > > - compatible > > + - "#address-cells" > > + - "#size-cells" > > + - ranges > > + > > +allOf: > > + - if: > > + properties: > > + xlnx,cluster-mode: > > + enum: > > + - 1 > > + then: > > + patternProperties: > > + "^r5f@[0-9a-f]+$": > > + type: object > > + > > + properties: > > + reg: > > + minItems: 1 > > + items: > > + - description: ATCM internal memory > > + - description: BTCM internal memory > > + - description: extra ATCM memory in lockstep mode > > + - description: extra BTCM memory in lockstep mode > > + > > + reg-names: > > + minItems: 1 > > + items: > > + - const: atcm0 > > + - const: btcm0 > > + - const: atcm1 > > + - const: btcm1 > > Why power domains are flexible? User may not want to use all the TCMs. For example, if users want to turn-on only TCM-A and rest of them want to keep off, then they can avoid having power-domains of other TCMs in the device-tree. This helps with less power-consumption when needed. Hence flexible list of power-domains list. I can certainly mention "items:" under power-domains property. > > > + > > + else: > > + patternProperties: > > + "^r5f@[0-9a-f]+$": > > + type: object > > + > > + properties: > > + reg: > > + minItems: 1 > > + items: > > + - description: ATCM internal memory > > + - description: BTCM internal memory > > + > > + reg-names: > > + minItems: 1 > > + items: > > + - const: atcm0 > > + - const: btcm0 > > + > > + power-domains: > > + maxItems: 3 > > Please list power domains. Okay. But minItems will be still what's mentioned above i.e. 2. I hope it's fine. > > > > > additionalProperties: false > > > Best regards, > Krzysztof >
On 11/03/2024 17:27, Tanmay Shah wrote: >>> + then: >>> + patternProperties: >>> + "^r5f@[0-9a-f]+$": >>> + type: object >>> + >>> + properties: >>> + reg: >>> + minItems: 1 >>> + items: >>> + - description: ATCM internal memory >>> + - description: BTCM internal memory >>> + - description: extra ATCM memory in lockstep mode >>> + - description: extra BTCM memory in lockstep mode >>> + >>> + reg-names: >>> + minItems: 1 >>> + items: >>> + - const: atcm0 >>> + - const: btcm0 >>> + - const: atcm1 >>> + - const: btcm1 >> >> Why power domains are flexible? > > User may not want to use all the TCMs. For example, if users want to turn-on only TCM-A and rest of them want to keep off, then > > they can avoid having power-domains of other TCMs in the device-tree. This helps with less power-consumption when needed. > > Hence flexible list of power-domains list. > Isn't turning on/off driver's job? Sorry, but what is "user" here? DTS describes bindings, not OS policy. Also, please wrap your replies to match email style. > I can certainly mention "items:" under power-domains property. > > >> Best regards, Krzysztof
On 3/12/24 7:10 AM, Krzysztof Kozlowski wrote: > On 11/03/2024 17:27, Tanmay Shah wrote: > >>> + then: > >>> + patternProperties: > >>> + "^r5f@[0-9a-f]+$": > >>> + type: object > >>> + > >>> + properties: > >>> + reg: > >>> + minItems: 1 > >>> + items: > >>> + - description: ATCM internal memory > >>> + - description: BTCM internal memory > >>> + - description: extra ATCM memory in lockstep mode > >>> + - description: extra BTCM memory in lockstep mode > >>> + > >>> + reg-names: > >>> + minItems: 1 > >>> + items: > >>> + - const: atcm0 > >>> + - const: btcm0 > >>> + - const: atcm1 > >>> + - const: btcm1 > >> > >> Why power domains are flexible? > > > > User may not want to use all the TCMs. For example, if users want to turn-on only TCM-A and rest of them want to keep off, then > > > > they can avoid having power-domains of other TCMs in the device-tree. This helps with less power-consumption when needed. > > > > Hence flexible list of power-domains list. > > > > Isn't turning on/off driver's job? Sorry, but what is "user" here? DTS > describes bindings, not OS policy. Thanks for reviews. Correct driver turns on off TCM. However, system designers (users) have option to not include TCM that is not needed in device-tree. So power-domains are flexible, same as reg, and reg-names. ATCM is always needed as vector table is in ATCM. R5 core power domain and ATCM power-domain for each core is always required so minItems 2. > Also, please wrap your replies to match email style. > > > I can certainly mention "items:" under power-domains property. > > > > > >> > > > Best regards, > Krzysztof >
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