The unaligned access checker only sets valid values for online cpus.
Check for these values on online cpus rather than on present cpus.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe")
---
 arch/riscv/kernel/traps_misaligned.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 8ded225e8c5b..c2ed4e689bf9 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -632,7 +632,7 @@ void unaligned_emulation_finish(void)
 	 * accesses emulated since tasks requesting such control can run on any
 	 * CPU.
 	 */
-	for_each_present_cpu(cpu) {
+	for_each_online_cpu(cpu) {
 		if (per_cpu(misaligned_access_speed, cpu) !=
 					RISCV_HWPROBE_MISALIGNED_EMULATED) {
 			return;

-- 
2.43.2

On Fri, Mar 01, 2024 at 05:45:33PM -0800, Charlie Jenkins wrote:
> The unaligned access checker only sets valid values for online cpus.
> Check for these values on online cpus rather than on present cpus.
> 
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe")

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  arch/riscv/kernel/traps_misaligned.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 8ded225e8c5b..c2ed4e689bf9 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -632,7 +632,7 @@ void unaligned_emulation_finish(void)
>  	 * accesses emulated since tasks requesting such control can run on any
>  	 * CPU.
>  	 */
> -	for_each_present_cpu(cpu) {
> +	for_each_online_cpu(cpu) {
>  		if (per_cpu(misaligned_access_speed, cpu) !=
>  					RISCV_HWPROBE_MISALIGNED_EMULATED) {
>  			return;

I went looking to see what the practical differences were between
"present" and "possible", cos I'd never really seen much code using
"present". Turns out present and possible are essentially the same on
riscv. TIL.