[PATCH V2] arm64/sysreg: Update ID_AA64DFR0_EL1 register

Anshuman Khandual posted 1 patch 1 year, 11 months ago
arch/arm64/tools/sysreg | 2 ++
1 file changed, 2 insertions(+)
[PATCH V2] arm64/sysreg: Update ID_AA64DFR0_EL1 register
Posted by Anshuman Khandual 1 year, 11 months ago
This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register
fields as per the definitions based on DDI0601 2023-12.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
This applies on v6.8-rc5

Changes in V2:

- Split ID_AA64DFR0_EL1 changes in this patch and updated PMSVer per Mark

Changes in V1:

https://lore.kernel.org/all/20240215055159.2440898-1-anshuman.khandual@arm.com/

 arch/arm64/tools/sysreg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a9cab2b730a3..508224a0e078 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1223,6 +1223,7 @@ UnsignedEnum	35:32	PMSVer
 	0b0010	V1P1
 	0b0011	V1P2
 	0b0100	V1P3
+	0b0101	V1P4
 EndEnum
 Field	31:28	CTX_CMPs
 Res0	27:24
@@ -1249,6 +1250,7 @@ UnsignedEnum	3:0	DebugVer
 	0b1000	V8P2
 	0b1001	V8P4
 	0b1010	V8P8
+	0b1011	V8P9
 EndEnum
 EndSysreg
 
-- 
2.25.1
Re: [PATCH V2] arm64/sysreg: Update ID_AA64DFR0_EL1 register
Posted by Catalin Marinas 1 year, 11 months ago
On Tue, 20 Feb 2024 09:18:29 +0530, Anshuman Khandual wrote:
> This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register
> fields as per the definitions based on DDI0601 2023-12.
> 
> 

Applied to arm64 (for-next/sysreg), thanks!

[1/1] arm64/sysreg: Update ID_AA64DFR0_EL1 register
      https://git.kernel.org/arm64/c/358fee291705

-- 
Catalin
Re: [PATCH V2] arm64/sysreg: Update ID_AA64DFR0_EL1 register
Posted by Mark Brown 1 year, 11 months ago
On Tue, Feb 20, 2024 at 09:18:29AM +0530, Anshuman Khandual wrote:
> This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register
> fields as per the definitions based on DDI0601 2023-12.

Reviewed-by: Mark Brown <broonie@kernel.org>

> @@ -1223,6 +1223,7 @@ UnsignedEnum	35:32	PMSVer
>  	0b0010	V1P1
>  	0b0011	V1P2
>  	0b0100	V1P3
> +	0b0101	V1P4
>  EndEnum

There's also a FEAT_SPE_SME documented in the text but not in the table
of enumerated values (I've reported this) - it makes sense to me to skip
this until the XML is internally consistent.

>  Field	31:28	CTX_CMPs
>  Res0	27:24
> @@ -1249,6 +1250,7 @@ UnsignedEnum	3:0	DebugVer
>  	0b1000	V8P2
>  	0b1001	V8P4
>  	0b1010	V8P8
> +	0b1011	V8P9
>  EndEnum

There's an IMPDEF value defined for this like the 32 bit equivalent but
that was a preexisting issue.