Documentation/arch/arm64/silicon-errata.rst | 7 +++++++ arch/arm64/include/asm/cputype.h | 4 ++++ arch/arm64/kernel/cpu_errata.c | 3 +++ 3 files changed, 14 insertions(+)
Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
suffers from all the same errata.
CC: Mark Rutland <mark.rutland@arm.com>
CC: Marc Zyngier <maz@kernel.org>
CC: Anshuman Khandual <anshuman.khandual@arm.com>
CC: stable@vger.kernel.org # 5.15+
Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
---
Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
arch/arm64/include/asm/cputype.h | 4 ++++
arch/arm64/kernel/cpu_errata.c | 3 +++
3 files changed, 14 insertions(+)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index e8c2ce1f9df6..45a7f4932fe0 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -243,3 +243,10 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ASR | ASR8601 | #8601001 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 7c7493cb571f..a632a7514e55 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -61,6 +61,7 @@
#define ARM_CPU_IMP_HISI 0x48
#define ARM_CPU_IMP_APPLE 0x61
#define ARM_CPU_IMP_AMPERE 0xC0
+#define ARM_CPU_IMP_MICROSOFT 0x6D
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -135,6 +136,8 @@
#define AMPERE_CPU_PART_AMPERE1 0xAC3
+#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
+
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
+#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100)
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 967c7c7a4e7d..76b8dd37092a 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2139208
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2119858
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
static const struct midr_range tsb_flush_fail_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2067961
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2054223
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
static struct midr_range trbe_write_out_of_range_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2253138
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2224489
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
--
2.34.1Hi Easwar, On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote: > Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft > implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore > suffers from all the same errata. Can you comment at all on where one might find this MIDR? That is, does your hypervisor report the native MIDR of the implementation or does it repaint it as an Arm Neoverse N2 (0x410FD490)? > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 7c7493cb571f..a632a7514e55 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -61,6 +61,7 @@ > #define ARM_CPU_IMP_HISI 0x48 > #define ARM_CPU_IMP_APPLE 0x61 > #define ARM_CPU_IMP_AMPERE 0xC0 > +#define ARM_CPU_IMP_MICROSOFT 0x6D > > #define ARM_CPU_PART_AEM_V8 0xD0F > #define ARM_CPU_PART_FOUNDATION 0xD00 > @@ -135,6 +136,8 @@ > > #define AMPERE_CPU_PART_AMPERE1 0xAC3 > > +#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ > + > #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) > #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) > #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) > @@ -193,6 +196,7 @@ > #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) > #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) > #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) > +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100) nitpick: consistently use the abbreviated 'MSFT' for all the definitions you're adding. -- Thanks, Oliver
On 2/12/2024 3:44 PM, Oliver Upton wrote: > Hi Easwar, > > On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote: >> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft >> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore >> suffers from all the same errata. > > Can you comment at all on where one might find this MIDR? That is, does > your hypervisor report the native MIDR of the implementation or does it > repaint it as an Arm Neoverse N2 (0x410FD490)? We will check on the Microsoft hypervisor's plans, and get back to you. Notwithstanding that, we do have baremetal use cases for Microsoft Azure Cobalt 100 as well where this MIDR value will show through. > >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h >> index 7c7493cb571f..a632a7514e55 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -61,6 +61,7 @@ >> #define ARM_CPU_IMP_HISI 0x48 >> #define ARM_CPU_IMP_APPLE 0x61 >> #define ARM_CPU_IMP_AMPERE 0xC0 >> +#define ARM_CPU_IMP_MICROSOFT 0x6D >> >> #define ARM_CPU_PART_AEM_V8 0xD0F >> #define ARM_CPU_PART_FOUNDATION 0xD00 >> @@ -135,6 +136,8 @@ >> >> #define AMPERE_CPU_PART_AMPERE1 0xAC3 >> >> +#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ >> + >> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) >> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) >> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) >> @@ -193,6 +196,7 @@ >> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) >> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) >> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) >> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100) > > nitpick: consistently use the abbreviated 'MSFT' for all the definitions > you're adding. > I was rather hoping to use Microsoft throughout, but I chose MSFT for the CPU_PART* to align columns with the other defines. :) If consistency is of a higher priority than column alignment, I can change it to MICROSOFT rather than MSFT throughout. Thanks, Easwar
On 2/13/2024 4:19 PM, Easwar Hariharan wrote: > On 2/12/2024 3:44 PM, Oliver Upton wrote: >> Hi Easwar, >> >> On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote: >>> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft >>> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore >>> suffers from all the same errata. >> >> Can you comment at all on where one might find this MIDR? That is, does >> your hypervisor report the native MIDR of the implementation or does it >> repaint it as an Arm Neoverse N2 (0x410FD490)? > > We will check on the Microsoft hypervisor's plans, and get back to you. > > Notwithstanding that, we do have baremetal use cases for Microsoft Azure Cobalt 100 > as well where this MIDR value will show through. > <snip> We checked in with our Microsoft hypervisor colleagues, and they do repaint the Azure Cobalt 100 as an Arm Neoverse N2, but again, we do have baremetal use cases. Thanks, Easwar
On Tue, Feb 13, 2024 at 04:19:08PM -0800, Easwar Hariharan wrote: > >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > >> index 7c7493cb571f..a632a7514e55 100644 > >> --- a/arch/arm64/include/asm/cputype.h > >> +++ b/arch/arm64/include/asm/cputype.h > >> @@ -61,6 +61,7 @@ > >> #define ARM_CPU_IMP_HISI 0x48 > >> #define ARM_CPU_IMP_APPLE 0x61 > >> #define ARM_CPU_IMP_AMPERE 0xC0 > >> +#define ARM_CPU_IMP_MICROSOFT 0x6D > >> > >> #define ARM_CPU_PART_AEM_V8 0xD0F > >> #define ARM_CPU_PART_FOUNDATION 0xD00 > >> @@ -135,6 +136,8 @@ > >> > >> #define AMPERE_CPU_PART_AMPERE1 0xAC3 > >> > >> +#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ > >> + > >> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) > >> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) > >> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) > >> @@ -193,6 +196,7 @@ > >> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) > >> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) > >> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) > >> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100) > > > > nitpick: consistently use the abbreviated 'MSFT' for all the definitions > > you're adding. > > I was rather hoping to use Microsoft throughout, but I chose MSFT for the CPU_PART* to align columns > with the other defines. :) If consistency is of a higher priority than column alignment, I can change it > to MICROSOFT rather than MSFT throughout. Consistency across the definitions is more important than alignmen; please choose either "MSFT" or "MICROSOFT" and use that consistently. Mark.
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