1. Patchew
  2. linux
  3. [PATCH v2 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts
  4. View patch

[PATCH v2 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts

Prabhakar posted 3 patches 2 years ago
[PATCH v2 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
Posted by Prabhakar 2 years ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts
supported by the IRQC block, reflect the same in DT binding doc.

- R9A07G043U              - RZ/G2UL
- R9A07G044L/R9A07G044LC  - RZ/{G2L,G2LC}
- R9A07G054               - RZ/V2L
- R9A08G045               - RZ/G3S

For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single
interrupt so we just use the below to represent them:
- ec7tie1-0
- ec7tie2-0
- ec7tiovf-0

Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts
were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045")
SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above)
support these interrupts. Therefore, mark the 'interrupt-names' property
as required for all the SoCs and update the example node in the binding
document.

Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../renesas,rzg2l-irqc.yaml                   | 44 +++++++++++++++----
 1 file changed, 35 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index d3b5aec0a3f7..078c538f8fbf 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -44,7 +44,7 @@ properties:
     maxItems: 1
 
   interrupts:
-    minItems: 41
+    minItems: 45
     items:
       - description: NMI interrupt
       - description: IRQ0 interrupt
@@ -88,9 +88,15 @@ properties:
       - description: GPIO interrupt, TINT30
       - description: GPIO interrupt, TINT31
       - description: Bus error interrupt
+      - description: ECCRAM0 1bit error interrupt
+      - description: ECCRAM0 2bit error interrupt
+      - description: ECCRAM0 error overflow interrupt
+      - description: ECCRAM1 1bit error interrupt
+      - description: ECCRAM1 2bit error interrupt
+      - description: ECCRAM1 error overflow interrupt
 
   interrupt-names:
-    minItems: 41
+    minItems: 45
     items:
       - const: nmi
       - const: irq0
@@ -134,6 +140,12 @@ properties:
       - const: tint30
       - const: tint31
       - const: bus-err
+      - const: ec7tie1-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
+      - const: ec7tie2-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
+      - const: ec7tiovf-0  # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
+      - const: ec7tie1-1
+      - const: ec7tie2-1
+      - const: ec7tiovf-1
 
   clocks:
     maxItems: 2
@@ -156,6 +168,7 @@ required:
   - interrupt-controller
   - reg
   - interrupts
+  - interrupt-names
   - clocks
   - clock-names
   - power-domains
@@ -169,16 +182,19 @@ allOf:
         compatible:
           contains:
             enum:
-              - renesas,r9a07g043u-irqc
               - renesas,r9a08g045-irqc
     then:
       properties:
         interrupts:
-          minItems: 42
+          maxItems: 45
         interrupt-names:
-          minItems: 42
-      required:
-        - interrupt-names
+          maxItems: 45
+    else:
+      properties:
+        interrupts:
+          minItems: 48
+        interrupt-names:
+          minItems: 48
 
 unevaluatedProperties: false
 
@@ -233,7 +249,14 @@ examples:
                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
-                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
         interrupt-names = "nmi",
                           "irq0", "irq1", "irq2", "irq3",
                           "irq4", "irq5", "irq6", "irq7",
@@ -244,7 +267,10 @@ examples:
                           "tint16", "tint17", "tint18", "tint19",
                           "tint20", "tint21", "tint22", "tint23",
                           "tint24", "tint25", "tint26", "tint27",
-                          "tint28", "tint29", "tint30", "tint31";
+                          "tint28", "tint29", "tint30", "tint31",
+                          "bus-err", "ec7tie1-0", "ec7tie2-0",
+                          "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+                          "ec7tiovf-1";
         clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
                  <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
         clock-names = "clk", "pclk";
-- 
2.34.1
Re: [PATCH v2 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
Posted by Geert Uytterhoeven 1 year, 12 months ago 
Hi Prabhakar,

On Mon, Feb 5, 2024 at 3:44 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts
> supported by the IRQC block, reflect the same in DT binding doc.
>
> - R9A07G043U              - RZ/G2UL
> - R9A07G044L/R9A07G044LC  - RZ/{G2L,G2LC}
> - R9A07G054               - RZ/V2L
> - R9A08G045               - RZ/G3S
>
> For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single
> interrupt so we just use the below to represent them:
> - ec7tie1-0
> - ec7tie2-0
> - ec7tiovf-0
>
> Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts
> were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045")
> SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above)
> support these interrupts. Therefore, mark the 'interrupt-names' property
> as required for all the SoCs and update the example node in the binding
> document.
>
> Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -88,9 +88,15 @@ properties:
>        - description: GPIO interrupt, TINT30
>        - description: GPIO interrupt, TINT31
>        - description: Bus error interrupt
> +      - description: ECCRAM0 1bit error interrupt
> +      - description: ECCRAM0 2bit error interrupt
> +      - description: ECCRAM0 error overflow interrupt
> +      - description: ECCRAM1 1bit error interrupt
> +      - description: ECCRAM1 2bit error interrupt
> +      - description: ECCRAM1 error overflow interrupt
>
>    interrupt-names:
> -    minItems: 41
> +    minItems: 45
>      items:
>        - const: nmi
>        - const: irq0
> @@ -134,6 +140,12 @@ properties:
>        - const: tint30
>        - const: tint31
>        - const: bus-err
> +      - const: ec7tie1-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> +      - const: ec7tie2-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> +      - const: ec7tiovf-0  # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.

These lines are indeed a bit long, and might become longer when newer
SoCs are introduced.

What about changing the descriptions instead, like

    -      - description: ECCRAM0 1bit error interrupt
    +      - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt

?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH v2 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
Posted by Lad, Prabhakar 1 year, 12 months ago 
Hi Geert,

Thank you for the review.

On Mon, Feb 12, 2024 at 4:25 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 5, 2024 at 3:44 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts
> > supported by the IRQC block, reflect the same in DT binding doc.
> >
> > - R9A07G043U              - RZ/G2UL
> > - R9A07G044L/R9A07G044LC  - RZ/{G2L,G2LC}
> > - R9A07G054               - RZ/V2L
> > - R9A08G045               - RZ/G3S
> >
> > For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single
> > interrupt so we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
> >
> > Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts
> > were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045")
> > SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above)
> > support these interrupts. Therefore, mark the 'interrupt-names' property
> > as required for all the SoCs and update the example node in the binding
> > document.
> >
> > Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> > Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -88,9 +88,15 @@ properties:
> >        - description: GPIO interrupt, TINT30
> >        - description: GPIO interrupt, TINT31
> >        - description: Bus error interrupt
> > +      - description: ECCRAM0 1bit error interrupt
> > +      - description: ECCRAM0 2bit error interrupt
> > +      - description: ECCRAM0 error overflow interrupt
> > +      - description: ECCRAM1 1bit error interrupt
> > +      - description: ECCRAM1 2bit error interrupt
> > +      - description: ECCRAM1 error overflow interrupt
> >
> >    interrupt-names:
> > -    minItems: 41
> > +    minItems: 45
> >      items:
> >        - const: nmi
> >        - const: irq0
> > @@ -134,6 +140,12 @@ properties:
> >        - const: tint30
> >        - const: tint31
> >        - const: bus-err
> > +      - const: ec7tie1-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> > +      - const: ec7tie2-0   # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
> > +      - const: ec7tiovf-0  # For RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts are combined into single interrupt.
>
> These lines are indeed a bit long, and might become longer when newer
> SoCs are introduced.
>
Agreed.

> What about changing the descriptions instead, like
>
>     -      - description: ECCRAM0 1bit error interrupt
>     +      - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
>
> ?
>
Agreed, sounds good. I'll just resend this patch fixing this.

Cheers,
Prabhakar
Re: [PATCH v2 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
Posted by Rob Herring 2 years ago 
On Mon, 05 Feb 2024 14:44:19 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts
> supported by the IRQC block, reflect the same in DT binding doc.
> 
> - R9A07G043U              - RZ/G2UL
> - R9A07G044L/R9A07G044LC  - RZ/{G2L,G2LC}
> - R9A07G054               - RZ/V2L
> - R9A08G045               - RZ/G3S
> 
> For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single
> interrupt so we just use the below to represent them:
> - ec7tie1-0
> - ec7tie2-0
> - ec7tiovf-0
> 
> Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts
> were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045")
> SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above)
> support these interrupts. Therefore, mark the 'interrupt-names' property
> as required for all the SoCs and update the example node in the binding
> document.
> 
> Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../renesas,rzg2l-irqc.yaml                   | 44 +++++++++++++++----
>  1 file changed, 35 insertions(+), 9 deletions(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml:143:111: [warning] line too long (114 > 110 characters) (line-length)
./Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml:144:111: [warning] line too long (114 > 110 characters) (line-length)
./Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml:145:111: [warning] line too long (114 > 110 characters) (line-length)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240205144421.51195-2-prabhakar.mahadev-lad.rj@bp.renesas.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.