On Thu, Jan 25, 2024 at 8:50 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>
> Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes
> FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit
> register accesses, otherwise a Serror Interrupt is raised. Do the write
> reg accesses in 32 bits.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
> drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 35a2d5554dfd..e887be6955a0 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1501,6 +1501,18 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
> .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> };
>
> +static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
> + .fifosize = 64,
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .clk_div = 4,
> + .high_speed = true,
> + .clk_from_cmu = true,
> + .has_loopback = true,
> + .use_32bit_io = true,
> + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
> static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
> .fifosize = 64,
> .rx_lvl_offset = 15,
> @@ -1556,6 +1568,10 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
> .compatible = "samsung,exynosautov9-spi",
> .data = &exynosautov9_spi_port_config,
> },
> + {
As I mentioned before, this braces style looks too bloated to me.
Other than that:
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
> + .compatible = "google,gs101-spi",
> + .data = &gs101_spi_port_config,
> + },
> {
> .compatible = "tesla,fsd-spi",
> .data = &fsd_spi_port_config,
> --
> 2.43.0.429.g432eaa2c6b-goog
>