This adds BRBE related register definitions and various other related field
macros there in. These will be used subsequently in a BRBE driver, which is
being added later on.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V16:
- Updated BRBINFx_EL1.TYPE = 0b110000 as field IMPDEF_TRAP_EL3
- Updated BRBCR_ELx[9] as field FZPSS
- Updated BRBINFINJ_EL1 to use sysreg field BRBINFx_EL1
arch/arm64/include/asm/sysreg.h | 109 ++++++++++++++++++++++++++
arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++
2 files changed, 240 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c3b19b376c86..72544b5c4951 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -272,6 +272,109 @@
#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
+#define __SYS_BRBINF(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 0))
+#define __SYS_BRBSRC(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 1))
+#define __SYS_BRBTGT(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 2))
+
+#define SYS_BRBINF0_EL1 __SYS_BRBINF(0)
+#define SYS_BRBINF1_EL1 __SYS_BRBINF(1)
+#define SYS_BRBINF2_EL1 __SYS_BRBINF(2)
+#define SYS_BRBINF3_EL1 __SYS_BRBINF(3)
+#define SYS_BRBINF4_EL1 __SYS_BRBINF(4)
+#define SYS_BRBINF5_EL1 __SYS_BRBINF(5)
+#define SYS_BRBINF6_EL1 __SYS_BRBINF(6)
+#define SYS_BRBINF7_EL1 __SYS_BRBINF(7)
+#define SYS_BRBINF8_EL1 __SYS_BRBINF(8)
+#define SYS_BRBINF9_EL1 __SYS_BRBINF(9)
+#define SYS_BRBINF10_EL1 __SYS_BRBINF(10)
+#define SYS_BRBINF11_EL1 __SYS_BRBINF(11)
+#define SYS_BRBINF12_EL1 __SYS_BRBINF(12)
+#define SYS_BRBINF13_EL1 __SYS_BRBINF(13)
+#define SYS_BRBINF14_EL1 __SYS_BRBINF(14)
+#define SYS_BRBINF15_EL1 __SYS_BRBINF(15)
+#define SYS_BRBINF16_EL1 __SYS_BRBINF(16)
+#define SYS_BRBINF17_EL1 __SYS_BRBINF(17)
+#define SYS_BRBINF18_EL1 __SYS_BRBINF(18)
+#define SYS_BRBINF19_EL1 __SYS_BRBINF(19)
+#define SYS_BRBINF20_EL1 __SYS_BRBINF(20)
+#define SYS_BRBINF21_EL1 __SYS_BRBINF(21)
+#define SYS_BRBINF22_EL1 __SYS_BRBINF(22)
+#define SYS_BRBINF23_EL1 __SYS_BRBINF(23)
+#define SYS_BRBINF24_EL1 __SYS_BRBINF(24)
+#define SYS_BRBINF25_EL1 __SYS_BRBINF(25)
+#define SYS_BRBINF26_EL1 __SYS_BRBINF(26)
+#define SYS_BRBINF27_EL1 __SYS_BRBINF(27)
+#define SYS_BRBINF28_EL1 __SYS_BRBINF(28)
+#define SYS_BRBINF29_EL1 __SYS_BRBINF(29)
+#define SYS_BRBINF30_EL1 __SYS_BRBINF(30)
+#define SYS_BRBINF31_EL1 __SYS_BRBINF(31)
+
+#define SYS_BRBSRC0_EL1 __SYS_BRBSRC(0)
+#define SYS_BRBSRC1_EL1 __SYS_BRBSRC(1)
+#define SYS_BRBSRC2_EL1 __SYS_BRBSRC(2)
+#define SYS_BRBSRC3_EL1 __SYS_BRBSRC(3)
+#define SYS_BRBSRC4_EL1 __SYS_BRBSRC(4)
+#define SYS_BRBSRC5_EL1 __SYS_BRBSRC(5)
+#define SYS_BRBSRC6_EL1 __SYS_BRBSRC(6)
+#define SYS_BRBSRC7_EL1 __SYS_BRBSRC(7)
+#define SYS_BRBSRC8_EL1 __SYS_BRBSRC(8)
+#define SYS_BRBSRC9_EL1 __SYS_BRBSRC(9)
+#define SYS_BRBSRC10_EL1 __SYS_BRBSRC(10)
+#define SYS_BRBSRC11_EL1 __SYS_BRBSRC(11)
+#define SYS_BRBSRC12_EL1 __SYS_BRBSRC(12)
+#define SYS_BRBSRC13_EL1 __SYS_BRBSRC(13)
+#define SYS_BRBSRC14_EL1 __SYS_BRBSRC(14)
+#define SYS_BRBSRC15_EL1 __SYS_BRBSRC(15)
+#define SYS_BRBSRC16_EL1 __SYS_BRBSRC(16)
+#define SYS_BRBSRC17_EL1 __SYS_BRBSRC(17)
+#define SYS_BRBSRC18_EL1 __SYS_BRBSRC(18)
+#define SYS_BRBSRC19_EL1 __SYS_BRBSRC(19)
+#define SYS_BRBSRC20_EL1 __SYS_BRBSRC(20)
+#define SYS_BRBSRC21_EL1 __SYS_BRBSRC(21)
+#define SYS_BRBSRC22_EL1 __SYS_BRBSRC(22)
+#define SYS_BRBSRC23_EL1 __SYS_BRBSRC(23)
+#define SYS_BRBSRC24_EL1 __SYS_BRBSRC(24)
+#define SYS_BRBSRC25_EL1 __SYS_BRBSRC(25)
+#define SYS_BRBSRC26_EL1 __SYS_BRBSRC(26)
+#define SYS_BRBSRC27_EL1 __SYS_BRBSRC(27)
+#define SYS_BRBSRC28_EL1 __SYS_BRBSRC(28)
+#define SYS_BRBSRC29_EL1 __SYS_BRBSRC(29)
+#define SYS_BRBSRC30_EL1 __SYS_BRBSRC(30)
+#define SYS_BRBSRC31_EL1 __SYS_BRBSRC(31)
+
+#define SYS_BRBTGT0_EL1 __SYS_BRBTGT(0)
+#define SYS_BRBTGT1_EL1 __SYS_BRBTGT(1)
+#define SYS_BRBTGT2_EL1 __SYS_BRBTGT(2)
+#define SYS_BRBTGT3_EL1 __SYS_BRBTGT(3)
+#define SYS_BRBTGT4_EL1 __SYS_BRBTGT(4)
+#define SYS_BRBTGT5_EL1 __SYS_BRBTGT(5)
+#define SYS_BRBTGT6_EL1 __SYS_BRBTGT(6)
+#define SYS_BRBTGT7_EL1 __SYS_BRBTGT(7)
+#define SYS_BRBTGT8_EL1 __SYS_BRBTGT(8)
+#define SYS_BRBTGT9_EL1 __SYS_BRBTGT(9)
+#define SYS_BRBTGT10_EL1 __SYS_BRBTGT(10)
+#define SYS_BRBTGT11_EL1 __SYS_BRBTGT(11)
+#define SYS_BRBTGT12_EL1 __SYS_BRBTGT(12)
+#define SYS_BRBTGT13_EL1 __SYS_BRBTGT(13)
+#define SYS_BRBTGT14_EL1 __SYS_BRBTGT(14)
+#define SYS_BRBTGT15_EL1 __SYS_BRBTGT(15)
+#define SYS_BRBTGT16_EL1 __SYS_BRBTGT(16)
+#define SYS_BRBTGT17_EL1 __SYS_BRBTGT(17)
+#define SYS_BRBTGT18_EL1 __SYS_BRBTGT(18)
+#define SYS_BRBTGT19_EL1 __SYS_BRBTGT(19)
+#define SYS_BRBTGT20_EL1 __SYS_BRBTGT(20)
+#define SYS_BRBTGT21_EL1 __SYS_BRBTGT(21)
+#define SYS_BRBTGT22_EL1 __SYS_BRBTGT(22)
+#define SYS_BRBTGT23_EL1 __SYS_BRBTGT(23)
+#define SYS_BRBTGT24_EL1 __SYS_BRBTGT(24)
+#define SYS_BRBTGT25_EL1 __SYS_BRBTGT(25)
+#define SYS_BRBTGT26_EL1 __SYS_BRBTGT(26)
+#define SYS_BRBTGT27_EL1 __SYS_BRBTGT(27)
+#define SYS_BRBTGT28_EL1 __SYS_BRBTGT(28)
+#define SYS_BRBTGT29_EL1 __SYS_BRBTGT(29)
+#define SYS_BRBTGT30_EL1 __SYS_BRBTGT(30)
+#define SYS_BRBTGT31_EL1 __SYS_BRBTGT(31)
+
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
@@ -794,6 +897,12 @@
#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
+/*
+ * BRBE Instructions
+ */
+#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
+#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
+
/* Common SCTLR_ELx flags. */
#define SCTLR_ELx_ENTP2 (BIT(60))
#define SCTLR_ELx_DSSBS (BIT(44))
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c9b67934367..caf851ba5dc0 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM
EndEnum
EndSysreg
+
+SysregFields BRBINFx_EL1
+Res0 63:47
+Field 46 CCU
+Field 45:32 CC
+Res0 31:18
+Field 17 LASTFAILED
+Field 16 T
+Res0 15:14
+Enum 13:8 TYPE
+ 0b000000 UNCOND_DIRECT
+ 0b000001 INDIRECT
+ 0b000010 DIRECT_LINK
+ 0b000011 INDIRECT_LINK
+ 0b000101 RET
+ 0b000111 ERET
+ 0b001000 COND_DIRECT
+ 0b100001 DEBUG_HALT
+ 0b100010 CALL
+ 0b100011 TRAP
+ 0b100100 SERROR
+ 0b100110 INSN_DEBUG
+ 0b100111 DATA_DEBUG
+ 0b101010 ALIGN_FAULT
+ 0b101011 INSN_FAULT
+ 0b101100 DATA_FAULT
+ 0b101110 IRQ
+ 0b101111 FIQ
+ 0b110000 IMPDEF_TRAP_EL3
+ 0b111001 DEBUG_EXIT
+EndEnum
+Enum 7:6 EL
+ 0b00 EL0
+ 0b01 EL1
+ 0b10 EL2
+ 0b11 EL3
+EndEnum
+Field 5 MPRED
+Res0 4:2
+Enum 1:0 VALID
+ 0b00 NONE
+ 0b01 TARGET
+ 0b10 SOURCE
+ 0b11 FULL
+EndEnum
+EndSysregFields
+
+SysregFields BRBCR_ELx
+Res0 63:24
+Field 23 EXCEPTION
+Field 22 ERTN
+Res0 21:10
+Field 9 FZPSS
+Field 8 FZP
+Res0 7
+Enum 6:5 TS
+ 0b01 VIRTUAL
+ 0b10 GUEST_PHYSICAL
+ 0b11 PHYSICAL
+EndEnum
+Field 4 MPRED
+Field 3 CC
+Res0 2
+Field 1 ExBRE
+Field 0 E0BRE
+EndSysregFields
+
+Sysreg BRBCR_EL2 2 4 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
+Sysreg BRBCR_EL1 2 1 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
+Sysreg BRBCR_EL12 2 5 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
+Sysreg BRBFCR_EL1 2 1 9 0 1
+Res0 63:30
+Enum 29:28 BANK
+ 0b0 FIRST
+ 0b1 SECOND
+EndEnum
+Res0 27:23
+Field 22 CONDDIR
+Field 21 DIRCALL
+Field 20 INDCALL
+Field 19 RTN
+Field 18 INDIRECT
+Field 17 DIRECT
+Field 16 EnI
+Res0 15:8
+Field 7 PAUSED
+Field 6 LASTFAILED
+Res0 5:0
+EndSysreg
+
+Sysreg BRBTS_EL1 2 1 9 0 2
+Field 63:0 TS
+EndSysreg
+
+Sysreg BRBINFINJ_EL1 2 1 9 1 0
+Fields BRBINFx_EL1
+EndSysreg
+
+Sysreg BRBSRCINJ_EL1 2 1 9 1 1
+Field 63:0 ADDRESS
+EndSysreg
+
+Sysreg BRBTGTINJ_EL1 2 1 9 1 2
+Field 63:0 ADDRESS
+EndSysreg
+
+Sysreg BRBIDR0_EL1 2 1 9 2 0
+Res0 63:16
+Enum 15:12 CC
+ 0b101 20_BIT
+EndEnum
+Enum 11:8 FORMAT
+ 0b0 0
+EndEnum
+Enum 7:0 NUMREC
+ 0b0001000 8
+ 0b0010000 16
+ 0b0100000 32
+ 0b1000000 64
+EndEnum
+EndSysreg
+
Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
Res0 63:60
UnsignedEnum 59:56 F64MM
--
2.25.1On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote:
> This adds BRBE related register definitions and various other related field
> macros there in. These will be used subsequently in a BRBE driver, which is
> being added later on.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V16:
>
> - Updated BRBINFx_EL1.TYPE = 0b110000 as field IMPDEF_TRAP_EL3
> - Updated BRBCR_ELx[9] as field FZPSS
> - Updated BRBINFINJ_EL1 to use sysreg field BRBINFx_EL1
>
> arch/arm64/include/asm/sysreg.h | 109 ++++++++++++++++++++++++++
> arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++
> 2 files changed, 240 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c3b19b376c86..72544b5c4951 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -272,6 +272,109 @@
>
> #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
>
> +#define __SYS_BRBINF(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 0))
> +#define __SYS_BRBSRC(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 1))
> +#define __SYS_BRBTGT(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 2))
We already have definitions for these since v6.5, added in commit:
57596c8f991c9aac ("arm64: Add debug registers affected by HDFGxTR_EL2:)
That commit also added register encoding definitions:
| #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
| #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
| #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
| #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
| #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
| #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
| #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
I don't think we need to add new encoding definitions for BRBINF<n>_EL1,
BRBSRC<n>_EL1, or BRBTGT<n>_EL1; we can just use those existing defintions
directly. That also means we don't need to add all of the expanded 0..31
definitions; the driver can use SYS_BRBINF_EL1(n) and friends directly.
[...]
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 4c9b67934367..caf851ba5dc0 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM
> EndEnum
> EndSysreg
>
> +
> +SysregFields BRBINFx_EL1
> +Res0 63:47
> +Field 46 CCU
> +Field 45:32 CC
> +Res0 31:18
> +Field 17 LASTFAILED
> +Field 16 T
> +Res0 15:14
> +Enum 13:8 TYPE
> + 0b000000 UNCOND_DIRECT
> + 0b000001 INDIRECT
> + 0b000010 DIRECT_LINK
> + 0b000011 INDIRECT_LINK
> + 0b000101 RET
> + 0b000111 ERET
> + 0b001000 COND_DIRECT
Minor nit, but for consistency with DIRECT_LINK, could we please use
DIRECT_UNCOND and DIRECT_COND?
> + 0b100001 DEBUG_HALT
> + 0b100010 CALL
> + 0b100011 TRAP
> + 0b100100 SERROR
> + 0b100110 INSN_DEBUG
> + 0b100111 DATA_DEBUG
> + 0b101010 ALIGN_FAULT
> + 0b101011 INSN_FAULT
> + 0b101100 DATA_FAULT
> + 0b101110 IRQ
> + 0b101111 FIQ
> + 0b110000 IMPDEF_TRAP_EL3
> + 0b111001 DEBUG_EXIT
That IMPDEF_TRAP_EL3 encoding doesn't seem to exist in the latest ARM ARM (ARM
DDI 0487J.a), and I see Mark Brown checked against the "Arm A-profile
Architecture Registers" document (ARM DDI 0601 ID121123, AKA 2023-12).
Could you please mention that in the commit message, and link to that version
of the document (https://developer.arm.com/documentation/ddi0601/2023-12/) ?
That'll make it easier for anyone else to review this, and it'll be good in
case anyone needs to figure out where this came from in future.
> +EndEnum
> +Enum 7:6 EL
> + 0b00 EL0
> + 0b01 EL1
> + 0b10 EL2
> + 0b11 EL3
> +EndEnum
> +Field 5 MPRED
> +Res0 4:2
> +Enum 1:0 VALID
> + 0b00 NONE
> + 0b01 TARGET
> + 0b10 SOURCE
> + 0b11 FULL
> +EndEnum
> +EndSysregFields
The other fields here all look good per the ARM ARM and sysreg document.
> +SysregFields BRBCR_ELx
> +Res0 63:24
> +Field 23 EXCEPTION
> +Field 22 ERTN
> +Res0 21:10
> +Field 9 FZPSS
> +Field 8 FZP
> +Res0 7
> +Enum 6:5 TS
> + 0b01 VIRTUAL
> + 0b10 GUEST_PHYSICAL
> + 0b11 PHYSICAL
> +EndEnum
> +Field 4 MPRED
> +Field 3 CC
> +Res0 2
> +Field 1 ExBRE
> +Field 0 E0BRE
> +EndSysregFields
This looks good per the ARM ARM and sysreg document.
> +Sysreg BRBCR_EL2 2 4 9 0 0
> +Fields BRBCR_ELx
> +EndSysreg
> +
> +Sysreg BRBCR_EL1 2 1 9 0 0
> +Fields BRBCR_ELx
> +EndSysreg
> +
> +Sysreg BRBCR_EL12 2 5 9 0 0
> +Fields BRBCR_ELx
> +EndSysreg
These all look good per the ARM ARM and sysreg document.
Minor nit, but could we please list thse in order:
BRBCR_EL1
BRBCR_EL12
BRBCR_EL2
... since that way the names are ordered alphnumerically, which is what we've
done for other groups (e.g. PIR_EL{1,12,2}), and it's the way the ARM ARM
happens to be ordered.
> +Sysreg BRBFCR_EL1 2 1 9 0 1
> +Res0 63:30
> +Enum 29:28 BANK
> + 0b0 FIRST
> + 0b1 SECOND
Nit: since this is a 2-bit field, please pad these as '0b00' and '0b01'.
Could we please use BANK_0 and BANK_1 rather than FIRST and SECOND?
That'd also be easier to use behind macros.
> +EndEnum
> +Res0 27:23
> +Field 22 CONDDIR
> +Field 21 DIRCALL
> +Field 20 INDCALL
> +Field 19 RTN
> +Field 18 INDIRECT
> +Field 17 DIRECT
> +Field 16 EnI
> +Res0 15:8
> +Field 7 PAUSED
> +Field 6 LASTFAILED
> +Res0 5:0
> +EndSysreg
Other than the nit, this looks good per the ARM ARM and sysreg document.
[...]
> +Sysreg BRBIDR0_EL1 2 1 9 2 0
> +Res0 63:16
> +Enum 15:12 CC
> + 0b101 20_BIT
> +EndEnum
> +Enum 11:8 FORMAT
> + 0b0 0
> +EndEnum
> +Enum 7:0 NUMREC
> + 0b0001000 8
> + 0b0010000 16
> + 0b0100000 32
> + 0b1000000 64
This is an 8-bit field; please pad these to 8 bits (they all need a leading
'0').
> +EndEnum
> +EndSysreg
Aside from the comments above, this looks good to me.
Mark.
On 2/21/24 19:22, Mark Rutland wrote:
> On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote:
>> This adds BRBE related register definitions and various other related field
>> macros there in. These will be used subsequently in a BRBE driver, which is
>> being added later on.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V16:
>>
>> - Updated BRBINFx_EL1.TYPE = 0b110000 as field IMPDEF_TRAP_EL3
>> - Updated BRBCR_ELx[9] as field FZPSS
>> - Updated BRBINFINJ_EL1 to use sysreg field BRBINFx_EL1
>>
>> arch/arm64/include/asm/sysreg.h | 109 ++++++++++++++++++++++++++
>> arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++
>> 2 files changed, 240 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index c3b19b376c86..72544b5c4951 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -272,6 +272,109 @@
>>
>> #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
>>
>> +#define __SYS_BRBINF(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 0))
>> +#define __SYS_BRBSRC(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 1))
>> +#define __SYS_BRBTGT(n) sys_reg(2, 1, 8, ((n) & 0xf), ((((n) & 0x10) >> 2) + 2))
>
> We already have definitions for these since v6.5, added in commit:
>
> 57596c8f991c9aac ("arm64: Add debug registers affected by HDFGxTR_EL2:)
>
> That commit also added register encoding definitions:
>
> | #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
> | #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
> | #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
> | #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
> | #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
> | #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
> | #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
>
> I don't think we need to add new encoding definitions for BRBINF<n>_EL1,
> BRBSRC<n>_EL1, or BRBTGT<n>_EL1; we can just use those existing defintions
> directly. That also means we don't need to add all of the expanded 0..31
> definitions; the driver can use SYS_BRBINF_EL1(n) and friends directly.
Right, that seems feasible. Hence with the following change to the BRBE driver
and arm64 KVM, we can convert using existing SYS_BRBXXX_EL1(n) format.
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 6a06dc2f0c06..739d861b9ef3 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1304,10 +1304,10 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
return 0;
}
-#define BRB_INF_SRC_TGT_EL1(n) \
- { SYS_DESC(SYS_BRBINF##n##_EL1), undef_access }, \
- { SYS_DESC(SYS_BRBSRC##n##_EL1), undef_access }, \
- { SYS_DESC(SYS_BRBTGT##n##_EL1), undef_access } \
+#define BRB_INF_SRC_TGT_EL1(n) \
+ { SYS_DESC(SYS_BRBINF_EL1(n)), undef_access }, \
+ { SYS_DESC(SYS_BRBSRC_EL1(n)), undef_access }, \
+ { SYS_DESC(SYS_BRBTGT_EL1(n)), undef_access } \
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
diff --git a/drivers/perf/arm_brbe.c b/drivers/perf/arm_brbe.c
index 22924023e0f1..dfaf098432ff 100644
--- a/drivers/perf/arm_brbe.c
+++ b/drivers/perf/arm_brbe.c
@@ -104,13 +104,13 @@ enum brbe_bank_idx {
};
#define RETURN_READ_BRBSRCN(n) \
- read_sysreg_s(SYS_BRBSRC##n##_EL1)
+ read_sysreg_s(SYS_BRBSRC_EL1(n))
#define RETURN_READ_BRBTGTN(n) \
- read_sysreg_s(SYS_BRBTGT##n##_EL1)
+ read_sysreg_s(SYS_BRBTGT_EL1(n))
#define RETURN_READ_BRBINFN(n) \
- read_sysreg_s(SYS_BRBINF##n##_EL1)
+ read_sysreg_s(SYS_BRBINF_EL1(n))
#define BRBE_REGN_CASE(n, case_macro) \
case n: return case_macro(n); break
But while here, will also drop previously added other BRBE registers
from (arch/arm64/include/asm/sysreg.h), as they are now being added
via (arch/arm64/tools/sysreg) instead which is the right place.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9a919a102cf1..481c7d186dfa 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -195,16 +195,8 @@
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
-#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
-#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
-#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
-#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
-
-#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
-#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
-#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
@@ -270,8 +262,6 @@
/* ETM */
#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
-#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
-
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
@@ -601,7 +591,6 @@
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
/* VHE encodings for architectural EL0/1 system registers */
-#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
>
> [...]
>
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index 4c9b67934367..caf851ba5dc0 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM
>> EndEnum
>> EndSysreg
>>
>> +
>> +SysregFields BRBINFx_EL1
>> +Res0 63:47
>> +Field 46 CCU
>> +Field 45:32 CC
>> +Res0 31:18
>> +Field 17 LASTFAILED
>> +Field 16 T
>> +Res0 15:14
>> +Enum 13:8 TYPE
>> + 0b000000 UNCOND_DIRECT
>> + 0b000001 INDIRECT
>> + 0b000010 DIRECT_LINK
>> + 0b000011 INDIRECT_LINK
>> + 0b000101 RET
>> + 0b000111 ERET
>> + 0b001000 COND_DIRECT
>
> Minor nit, but for consistency with DIRECT_LINK, could we please use
> DIRECT_UNCOND and DIRECT_COND?
Sure, will change as above.
>
>> + 0b100001 DEBUG_HALT
>> + 0b100010 CALL
>> + 0b100011 TRAP
>> + 0b100100 SERROR
>> + 0b100110 INSN_DEBUG
>> + 0b100111 DATA_DEBUG
>> + 0b101010 ALIGN_FAULT
>> + 0b101011 INSN_FAULT
>> + 0b101100 DATA_FAULT
>> + 0b101110 IRQ
>> + 0b101111 FIQ
>> + 0b110000 IMPDEF_TRAP_EL3
>> + 0b111001 DEBUG_EXIT
>
> That IMPDEF_TRAP_EL3 encoding doesn't seem to exist in the latest ARM ARM (ARM
> DDI 0487J.a), and I see Mark Brown checked against the "Arm A-profile
> Architecture Registers" document (ARM DDI 0601 ID121123, AKA 2023-12).
That's correct.
>
> Could you please mention that in the commihttps://developer.arm.com/documentation/ddi0601/2023-12/) ?
> That'll make it easier for anyone else to review this, and it'll be good it message, and link to that version
> of the document (n
> case anyone needs to figure out where this came from in future.
>
Sure, will do that.
>> +EndEnum
>> +Enum 7:6 EL
>> + 0b00 EL0
>> + 0b01 EL1
>> + 0b10 EL2
>> + 0b11 EL3
>> +EndEnum
>> +Field 5 MPRED
>> +Res0 4:2
>> +Enum 1:0 VALID
>> + 0b00 NONE
>> + 0b01 TARGET
>> + 0b10 SOURCE
>> + 0b11 FULL
>> +EndEnum
>> +EndSysregFields
>
> The other fields here all look good per the ARM ARM and sysreg document.
>
>> +SysregFields BRBCR_ELx
>> +Res0 63:24
>> +Field 23 EXCEPTION
>> +Field 22 ERTN
>> +Res0 21:10
>> +Field 9 FZPSS
>> +Field 8 FZP
>> +Res0 7
>> +Enum 6:5 TS
>> + 0b01 VIRTUAL
>> + 0b10 GUEST_PHYSICAL
>> + 0b11 PHYSICAL
>> +EndEnum
>> +Field 4 MPRED
>> +Field 3 CC
>> +Res0 2
>> +Field 1 ExBRE
>> +Field 0 E0BRE
>> +EndSysregFields
>
> This looks good per the ARM ARM and sysreg document.
>
>> +Sysreg BRBCR_EL2 2 4 9 0 0
>> +Fields BRBCR_ELx
>> +EndSysreg
>> +
>> +Sysreg BRBCR_EL1 2 1 9 0 0
>> +Fields BRBCR_ELx
>> +EndSysreg
>> +
>> +Sysreg BRBCR_EL12 2 5 9 0 0
>> +Fields BRBCR_ELx
>> +EndSysreg
>
> These all look good per the ARM ARM and sysreg document.
>
> Minor nit, but could we please list thse in order:
>
> BRBCR_EL1
> BRBCR_EL12
> BRBCR_EL2
>
> ... since that way the names are ordered alphnumerically, which is what we've
> done for other groups (e.g. PIR_EL{1,12,2}), and it's the way the ARM ARM
> happens to be ordered.
>
>> +Sysreg BRBFCR_EL1 2 1 9 0 1
>> +Res0 63:30
>> +Enum 29:28 BANK
>> + 0b0 FIRST
>> + 0b1 SECOND
>
> Nit: since this is a 2-bit field, please pad these as '0b00' and '0b01'.
>
> Could we please use BANK_0 and BANK_1 rather than FIRST and SECOND?
>
> That'd also be easier to use behind macros.
Sure, will change as above.
>
>> +EndEnum
>> +Res0 27:23
>> +Field 22 CONDDIR
>> +Field 21 DIRCALL
>> +Field 20 INDCALL
>> +Field 19 RTN
>> +Field 18 INDIRECT
>> +Field 17 DIRECT
>> +Field 16 EnI
>> +Res0 15:8
>> +Field 7 PAUSED
>> +Field 6 LASTFAILED
>> +Res0 5:0
>> +EndSysreg
>
> Other than the nit, this looks good per the ARM ARM and sysreg document.
Okay
>
> [...]
>
>> +Sysreg BRBIDR0_EL1 2 1 9 2 0
>> +Res0 63:16
>> +Enum 15:12 CC
>> + 0b101 20_BIT
>> +EndEnum
>> +Enum 11:8 FORMAT
>> + 0b0 0
>> +EndEnum
>> +Enum 7:0 NUMREC
>> + 0b0001000 8
>> + 0b0010000 16
>> + 0b0100000 32
>> + 0b1000000 64
>
> This is an 8-bit field; please pad these to 8 bits (they all need a leading
> '0').
Sure, will change as above.
>
>> +EndEnum
>> +EndSysreg
>
> Aside from the comments above, this looks good to me.
>
> Mark.
On Wed, Feb 21, 2024 at 01:52:38PM +0000, Mark Rutland wrote:
> On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote:
> Minor nit, but could we please list thse in order:
> BRBCR_EL1
> BRBCR_EL12
> BRBCR_EL2
> ... since that way the names are ordered alphnumerically, which is what we've
> done for other groups (e.g. PIR_EL{1,12,2}), and it's the way the ARM ARM
> happens to be ordered.
It's a good point about the sorting, though the file is currently mostly
sorted by encoding rather than alphanumerically (similarly to how
sysreg.h was done).
On Wed, Feb 21, 2024 at 01:59:03PM +0000, Mark Brown wrote:
> On Wed, Feb 21, 2024 at 01:52:38PM +0000, Mark Rutland wrote:
> > On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote:
>
> > Minor nit, but could we please list thse in order:
>
> > BRBCR_EL1
> > BRBCR_EL12
> > BRBCR_EL2
>
> > ... since that way the names are ordered alphnumerically, which is what we've
> > done for other groups (e.g. PIR_EL{1,12,2}), and it's the way the ARM ARM
> > happens to be ordered.
>
> It's a good point about the sorting, though the file is currently mostly
> sorted by encoding rather than alphanumerically (similarly to how
> sysreg.h was done).
Sure, we're inconsistent. I'd just prefer that there's *some* local ordering
here, as the patch is neither ordered as above nor by encoding:
Sysreg BRBCR_EL2 2 4 9 0 0
...
Sysreg BRBCR_EL1 2 1 9 0 0
...
Sysreg BRBCR_EL12 2 5 9 0 0
Mark.
On Wed, Feb 21, 2024 at 02:05:24PM +0000, Mark Rutland wrote: > On Wed, Feb 21, 2024 at 01:59:03PM +0000, Mark Brown wrote: > > On Wed, Feb 21, 2024 at 01:52:38PM +0000, Mark Rutland wrote: > > It's a good point about the sorting, though the file is currently mostly > > sorted by encoding rather than alphanumerically (similarly to how > > sysreg.h was done). > Sure, we're inconsistent. I'd just prefer that there's *some* local ordering > here, as the patch is neither ordered as above nor by encoding: I agree, I'm just saying that if we're going to fix the ordering it'd probably be better to go along with what the rest of the file is doing.
On 2/21/24 19:37, Mark Brown wrote: > On Wed, Feb 21, 2024 at 02:05:24PM +0000, Mark Rutland wrote: >> On Wed, Feb 21, 2024 at 01:59:03PM +0000, Mark Brown wrote: >>> On Wed, Feb 21, 2024 at 01:52:38PM +0000, Mark Rutland wrote: > >>> It's a good point about the sorting, though the file is currently mostly >>> sorted by encoding rather than alphanumerically (similarly to how >>> sysreg.h was done). > >> Sure, we're inconsistent. I'd just prefer that there's *some* local ordering >> here, as the patch is neither ordered as above nor by encoding: > > I agree, I'm just saying that if we're going to fix the ordering it'd > probably be better to go along with what the rest of the file is doing. Sure, will change the registers order as has been suggested earlier i.e alphanumerically instead. Because ordering registers with encoding will push BRBCR_EL2/12 after all other BRBE registers, including BRBIDR0_EL1. After the change BRBCR_EL1 BRBCR_EL12 BRBCR_EL2
On Fri, Feb 23, 2024 at 10:58:12AM +0530, Anshuman Khandual wrote: > On 2/21/24 19:37, Mark Brown wrote: > > On Wed, Feb 21, 2024 at 02:05:24PM +0000, Mark Rutland wrote: > >> Sure, we're inconsistent. I'd just prefer that there's *some* local ordering > >> here, as the patch is neither ordered as above nor by encoding: > > I agree, I'm just saying that if we're going to fix the ordering it'd > > probably be better to go along with what the rest of the file is doing. > Sure, will change the registers order as has been suggested earlier i.e > alphanumerically instead. Because ordering registers with encoding will > push BRBCR_EL2/12 after all other BRBE registers, including BRBIDR0_EL1. > After the change > BRBCR_EL1 > BRBCR_EL12 > BRBCR_EL2 The _EL2/12 registers generally come at the end of the file due to the way the encodings work?
On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote: > This adds BRBE related register definitions and various other related field > macros there in. These will be used subsequently in a BRBE driver, which is > being added later on. Checked against DDI0601 2023-12. Reviewed-by: Mark Brown <broonie@kernel.org>
This adds BRBE related register definitions and various other related field
macros there in. These will be used subsequently in a BRBE driver, which is
being added later on. While here, this drops redundant register definitions
from the header i.e (arch/arm64/include/asm/sysreg.h).
BRBINFx_EL1_TYPE_IMPDEF_TRAP_EL3 register field value has been derived from
latest ARM DDI 0601 ID121123, AKA 2023-12 instead of latest ARM ARM i.e ARM
DDI 0487J.a. Please find the definition here.
https://developer.arm.com/documentation/ddi0601/2023-12/
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Please find the modified patch here for a quick review and do let me know
if this looks good for the next version i.e V17. BRBCR_EL1/12/2 organized
per their encoding. Thanks !
arch/arm64/include/asm/sysreg.h | 17 ++---
arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++
2 files changed, 137 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c3b19b376c86..481c7d186dfa 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -195,16 +195,8 @@
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
-#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
-#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
-#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
-#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
-
-#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
-#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
-#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
@@ -270,8 +262,6 @@
/* ETM */
#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
-#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
-
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
@@ -601,7 +591,6 @@
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
/* VHE encodings for architectural EL0/1 system registers */
-#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
@@ -794,6 +783,12 @@
#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
+/*
+ * BRBE Instructions
+ */
+#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
+#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
+
/* Common SCTLR_ELx flags. */
#define SCTLR_ELx_ENTP2 (BIT(60))
#define SCTLR_ELx_DSSBS (BIT(44))
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c9b67934367..60d288cbd5eb 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM
EndEnum
EndSysreg
+
+SysregFields BRBINFx_EL1
+Res0 63:47
+Field 46 CCU
+Field 45:32 CC
+Res0 31:18
+Field 17 LASTFAILED
+Field 16 T
+Res0 15:14
+Enum 13:8 TYPE
+ 0b000000 DIRECT_UNCOND
+ 0b000001 INDIRECT
+ 0b000010 DIRECT_LINK
+ 0b000011 INDIRECT_LINK
+ 0b000101 RET
+ 0b000111 ERET
+ 0b001000 DIRECT_COND
+ 0b100001 DEBUG_HALT
+ 0b100010 CALL
+ 0b100011 TRAP
+ 0b100100 SERROR
+ 0b100110 INSN_DEBUG
+ 0b100111 DATA_DEBUG
+ 0b101010 ALIGN_FAULT
+ 0b101011 INSN_FAULT
+ 0b101100 DATA_FAULT
+ 0b101110 IRQ
+ 0b101111 FIQ
+ 0b110000 IMPDEF_TRAP_EL3
+ 0b111001 DEBUG_EXIT
+EndEnum
+Enum 7:6 EL
+ 0b00 EL0
+ 0b01 EL1
+ 0b10 EL2
+ 0b11 EL3
+EndEnum
+Field 5 MPRED
+Res0 4:2
+Enum 1:0 VALID
+ 0b00 NONE
+ 0b01 TARGET
+ 0b10 SOURCE
+ 0b11 FULL
+EndEnum
+EndSysregFields
+
+SysregFields BRBCR_ELx
+Res0 63:24
+Field 23 EXCEPTION
+Field 22 ERTN
+Res0 21:10
+Field 9 FZPSS
+Field 8 FZP
+Res0 7
+Enum 6:5 TS
+ 0b01 VIRTUAL
+ 0b10 GUEST_PHYSICAL
+ 0b11 PHYSICAL
+EndEnum
+Field 4 MPRED
+Field 3 CC
+Res0 2
+Field 1 ExBRE
+Field 0 E0BRE
+EndSysregFields
+
+Sysreg BRBCR_EL1 2 1 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
+Sysreg BRBFCR_EL1 2 1 9 0 1
+Res0 63:30
+Enum 29:28 BANK
+ 0b00 BANK_0
+ 0b01 BANK_1
+EndEnum
+Res0 27:23
+Field 22 CONDDIR
+Field 21 DIRCALL
+Field 20 INDCALL
+Field 19 RTN
+Field 18 INDIRECT
+Field 17 DIRECT
+Field 16 EnI
+Res0 15:8
+Field 7 PAUSED
+Field 6 LASTFAILED
+Res0 5:0
+EndSysreg
+
+Sysreg BRBTS_EL1 2 1 9 0 2
+Field 63:0 TS
+EndSysreg
+
+Sysreg BRBINFINJ_EL1 2 1 9 1 0
+Fields BRBINFx_EL1
+EndSysreg
+
+Sysreg BRBSRCINJ_EL1 2 1 9 1 1
+Field 63:0 ADDRESS
+EndSysreg
+
+Sysreg BRBTGTINJ_EL1 2 1 9 1 2
+Field 63:0 ADDRESS
+EndSysreg
+
+Sysreg BRBIDR0_EL1 2 1 9 2 0
+Res0 63:16
+Enum 15:12 CC
+ 0b101 20_BIT
+EndEnum
+Enum 11:8 FORMAT
+ 0b0 0
+EndEnum
+Enum 7:0 NUMREC
+ 0b00001000 8
+ 0b00010000 16
+ 0b00100000 32
+ 0b01000000 64
+EndEnum
+EndSysreg
+
+Sysreg BRBCR_EL2 2 4 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
+Sysreg BRBCR_EL12 2 5 9 0 0
+Fields BRBCR_ELx
+EndSysreg
+
Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
Res0 63:60
UnsignedEnum 59:56 F64MM
--
2.25.1On Mon, Feb 26, 2024 at 09:54:41AM +0530, Anshuman Khandual wrote: > This adds BRBE related register definitions and various other related field > macros there in. These will be used subsequently in a BRBE driver, which is > being added later on. While here, this drops redundant register definitions > from the header i.e (arch/arm64/include/asm/sysreg.h). > > BRBINFx_EL1_TYPE_IMPDEF_TRAP_EL3 register field value has been derived from > latest ARM DDI 0601 ID121123, AKA 2023-12 instead of latest ARM ARM i.e ARM > DDI 0487J.a. Please find the definition here. > > https://developer.arm.com/documentation/ddi0601/2023-12/ > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > Please find the modified patch here for a quick review and do let me know > if this looks good for the next version i.e V17. BRBCR_EL1/12/2 organized > per their encoding. Thanks ! Superficially that looks fine to me. Mark. > arch/arm64/include/asm/sysreg.h | 17 ++--- > arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++ > 2 files changed, 137 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index c3b19b376c86..481c7d186dfa 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -195,16 +195,8 @@ > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) > > #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) > -#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) > #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) > -#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) > #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) > -#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) > -#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) > - > -#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) > -#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) > -#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) > > #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) > #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) > @@ -270,8 +262,6 @@ > /* ETM */ > #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) > > -#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) > - > #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) > #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) > #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) > @@ -601,7 +591,6 @@ > #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) > > /* VHE encodings for architectural EL0/1 system registers */ > -#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) > #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) > #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) > #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) > @@ -794,6 +783,12 @@ > #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) > #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) > > +/* > + * BRBE Instructions > + */ > +#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f)) > +#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f)) > + > /* Common SCTLR_ELx flags. */ > #define SCTLR_ELx_ENTP2 (BIT(60)) > #define SCTLR_ELx_DSSBS (BIT(44)) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 4c9b67934367..60d288cbd5eb 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM > EndEnum > EndSysreg > > + > +SysregFields BRBINFx_EL1 > +Res0 63:47 > +Field 46 CCU > +Field 45:32 CC > +Res0 31:18 > +Field 17 LASTFAILED > +Field 16 T > +Res0 15:14 > +Enum 13:8 TYPE > + 0b000000 DIRECT_UNCOND > + 0b000001 INDIRECT > + 0b000010 DIRECT_LINK > + 0b000011 INDIRECT_LINK > + 0b000101 RET > + 0b000111 ERET > + 0b001000 DIRECT_COND > + 0b100001 DEBUG_HALT > + 0b100010 CALL > + 0b100011 TRAP > + 0b100100 SERROR > + 0b100110 INSN_DEBUG > + 0b100111 DATA_DEBUG > + 0b101010 ALIGN_FAULT > + 0b101011 INSN_FAULT > + 0b101100 DATA_FAULT > + 0b101110 IRQ > + 0b101111 FIQ > + 0b110000 IMPDEF_TRAP_EL3 > + 0b111001 DEBUG_EXIT > +EndEnum > +Enum 7:6 EL > + 0b00 EL0 > + 0b01 EL1 > + 0b10 EL2 > + 0b11 EL3 > +EndEnum > +Field 5 MPRED > +Res0 4:2 > +Enum 1:0 VALID > + 0b00 NONE > + 0b01 TARGET > + 0b10 SOURCE > + 0b11 FULL > +EndEnum > +EndSysregFields > + > +SysregFields BRBCR_ELx > +Res0 63:24 > +Field 23 EXCEPTION > +Field 22 ERTN > +Res0 21:10 > +Field 9 FZPSS > +Field 8 FZP > +Res0 7 > +Enum 6:5 TS > + 0b01 VIRTUAL > + 0b10 GUEST_PHYSICAL > + 0b11 PHYSICAL > +EndEnum > +Field 4 MPRED > +Field 3 CC > +Res0 2 > +Field 1 ExBRE > +Field 0 E0BRE > +EndSysregFields > + > +Sysreg BRBCR_EL1 2 1 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > +Sysreg BRBFCR_EL1 2 1 9 0 1 > +Res0 63:30 > +Enum 29:28 BANK > + 0b00 BANK_0 > + 0b01 BANK_1 > +EndEnum > +Res0 27:23 > +Field 22 CONDDIR > +Field 21 DIRCALL > +Field 20 INDCALL > +Field 19 RTN > +Field 18 INDIRECT > +Field 17 DIRECT > +Field 16 EnI > +Res0 15:8 > +Field 7 PAUSED > +Field 6 LASTFAILED > +Res0 5:0 > +EndSysreg > + > +Sysreg BRBTS_EL1 2 1 9 0 2 > +Field 63:0 TS > +EndSysreg > + > +Sysreg BRBINFINJ_EL1 2 1 9 1 0 > +Fields BRBINFx_EL1 > +EndSysreg > + > +Sysreg BRBSRCINJ_EL1 2 1 9 1 1 > +Field 63:0 ADDRESS > +EndSysreg > + > +Sysreg BRBTGTINJ_EL1 2 1 9 1 2 > +Field 63:0 ADDRESS > +EndSysreg > + > +Sysreg BRBIDR0_EL1 2 1 9 2 0 > +Res0 63:16 > +Enum 15:12 CC > + 0b101 20_BIT > +EndEnum > +Enum 11:8 FORMAT > + 0b0 0 > +EndEnum > +Enum 7:0 NUMREC > + 0b00001000 8 > + 0b00010000 16 > + 0b00100000 32 > + 0b01000000 64 > +EndEnum > +EndSysreg > + > +Sysreg BRBCR_EL2 2 4 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > +Sysreg BRBCR_EL12 2 5 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 > Res0 63:60 > UnsignedEnum 59:56 F64MM > -- > 2.25.1 >
On Mon, Feb 26, 2024 at 09:54:41AM +0530, Anshuman Khandual wrote: > Please find the modified patch here for a quick review and do let me know > if this looks good for the next version i.e V17. BRBCR_EL1/12/2 organized > per their encoding. Thanks ! That looks good to me from a quick scan.
Both platform i.e ARM_BREAKPOINT_LEN_X and generic i.e HW_BREAKPOINT_LEN_X
macros are used interchangeably to convert event->attr.bp_len and platform
breakpoint control arch_hw_breakpoint_ctrl->len. Let's be consistent while
deriving one from the other. This does not cause any functional changes.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
This applies on v6.8-rc5
arch/arm64/kernel/hw_breakpoint.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index 35225632d70a..1ab9fc865ddd 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -301,28 +301,28 @@ static int get_hbp_len(u8 hbp_len)
switch (hbp_len) {
case ARM_BREAKPOINT_LEN_1:
- len_in_bytes = 1;
+ len_in_bytes = HW_BREAKPOINT_LEN_1;
break;
case ARM_BREAKPOINT_LEN_2:
- len_in_bytes = 2;
+ len_in_bytes = HW_BREAKPOINT_LEN_2;
break;
case ARM_BREAKPOINT_LEN_3:
- len_in_bytes = 3;
+ len_in_bytes = HW_BREAKPOINT_LEN_3;
break;
case ARM_BREAKPOINT_LEN_4:
- len_in_bytes = 4;
+ len_in_bytes = HW_BREAKPOINT_LEN_4;
break;
case ARM_BREAKPOINT_LEN_5:
- len_in_bytes = 5;
+ len_in_bytes = HW_BREAKPOINT_LEN_5;
break;
case ARM_BREAKPOINT_LEN_6:
- len_in_bytes = 6;
+ len_in_bytes = HW_BREAKPOINT_LEN_6;
break;
case ARM_BREAKPOINT_LEN_7:
- len_in_bytes = 7;
+ len_in_bytes = HW_BREAKPOINT_LEN_7;
break;
case ARM_BREAKPOINT_LEN_8:
- len_in_bytes = 8;
+ len_in_bytes = HW_BREAKPOINT_LEN_8;
break;
}
--
2.25.1
On 2/26/24 09:52, Anshuman Khandual wrote:
> Both platform i.e ARM_BREAKPOINT_LEN_X and generic i.e HW_BREAKPOINT_LEN_X
> macros are used interchangeably to convert event->attr.bp_len and platform
> breakpoint control arch_hw_breakpoint_ctrl->len. Let's be consistent while
> deriving one from the other. This does not cause any functional changes.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> This applies on v6.8-rc5
>
> arch/arm64/kernel/hw_breakpoint.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
> index 35225632d70a..1ab9fc865ddd 100644
> --- a/arch/arm64/kernel/hw_breakpoint.c
> +++ b/arch/arm64/kernel/hw_breakpoint.c
> @@ -301,28 +301,28 @@ static int get_hbp_len(u8 hbp_len)
>
> switch (hbp_len) {
> case ARM_BREAKPOINT_LEN_1:
> - len_in_bytes = 1;
> + len_in_bytes = HW_BREAKPOINT_LEN_1;
> break;
> case ARM_BREAKPOINT_LEN_2:
> - len_in_bytes = 2;
> + len_in_bytes = HW_BREAKPOINT_LEN_2;
> break;
> case ARM_BREAKPOINT_LEN_3:
> - len_in_bytes = 3;
> + len_in_bytes = HW_BREAKPOINT_LEN_3;
> break;
> case ARM_BREAKPOINT_LEN_4:
> - len_in_bytes = 4;
> + len_in_bytes = HW_BREAKPOINT_LEN_4;
> break;
> case ARM_BREAKPOINT_LEN_5:
> - len_in_bytes = 5;
> + len_in_bytes = HW_BREAKPOINT_LEN_5;
> break;
> case ARM_BREAKPOINT_LEN_6:
> - len_in_bytes = 6;
> + len_in_bytes = HW_BREAKPOINT_LEN_6;
> break;
> case ARM_BREAKPOINT_LEN_7:
> - len_in_bytes = 7;
> + len_in_bytes = HW_BREAKPOINT_LEN_7;
> break;
> case ARM_BREAKPOINT_LEN_8:
> - len_in_bytes = 8;
> + len_in_bytes = HW_BREAKPOINT_LEN_8;
> break;
> }
>
Please ignore this. Wrong patch got picked up in the git send-email :)
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