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[PATCH 5/7] spi: s3c64xx: Add Exynos850 support

Sam Protsenko posted 7 patches 1 year, 11 months ago
There is a newer version of this series
[PATCH 5/7] spi: s3c64xx: Add Exynos850 support
Posted by Sam Protsenko 1 year, 11 months ago 
Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
can be configured in SPI mode:

  * spi_0: BLK_PERI_SPI_0 (0x13940000)
  * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
  * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)

SPI FIFO depth is 64 bytes for all those SPI blocks, so the
.fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
default internal clock divider, and an internal loopback mode to run
a loopback test.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
 drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 0e48ffd499b9..f7d623ad6ac3 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
 };
 
+static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
+	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f },
+	.rx_lvl_offset	= 15,
+	.tx_st_done	= 25,
+	.clk_div	= 4,
+	.high_speed	= true,
+	.clk_from_cmu	= true,
+	.has_loopback	= true,
+	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
 	.fifo_lvl_mask	= { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
 			    0x7f, 0x7f, 0x7f, 0x7f},
@@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
 	{ .compatible = "samsung,exynos5433-spi",
 			.data = (void *)&exynos5433_spi_port_config,
 	},
+	{ .compatible = "samsung,exynos850-spi",
+			.data = (void *)&exynos850_spi_port_config,
+	},
 	{ .compatible = "samsung,exynosautov9-spi",
 			.data = (void *)&exynosautov9_spi_port_config,
 	},
-- 
2.39.2
Re: [PATCH 5/7] spi: s3c64xx: Add Exynos850 support
Posted by Tudor Ambarus 1 year, 11 months ago 

On 1/20/24 01:29, Sam Protsenko wrote:
> Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
> can be configured in SPI mode:
> 
>   * spi_0: BLK_PERI_SPI_0 (0x13940000)
>   * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
>   * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)
> 
> SPI FIFO depth is 64 bytes for all those SPI blocks, so the
> .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
> default internal clock divider, and an internal loopback mode to run
> a loopback test.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> ---
>  drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 0e48ffd499b9..f7d623ad6ac3 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
>  	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
>  };
>  
> +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
> +	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f },

I'll come with a follow up patch on top of this. Having the dt alias
used as an index in the fifo_lvl_mask to determine the FIFO depth is
wrong. Not only because of the dependency on the alias, but also because
the fifo_lvl_mask value does not reflect the FIFO level reg field.
Playing with what we have now is ok by me, I find the patch good.

> +	.rx_lvl_offset	= 15,
> +	.tx_st_done	= 25,
> +	.clk_div	= 4,
> +	.high_speed	= true,
> +	.clk_from_cmu	= true,
> +	.has_loopback	= true,
> +	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
>  static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
>  	.fifo_lvl_mask	= { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
>  			    0x7f, 0x7f, 0x7f, 0x7f},
> @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
>  	{ .compatible = "samsung,exynos5433-spi",
>  			.data = (void *)&exynos5433_spi_port_config,
>  	},
> +	{ .compatible = "samsung,exynos850-spi",
> +			.data = (void *)&exynos850_spi_port_config,
> +	},
>  	{ .compatible = "samsung,exynosautov9-spi",
>  			.data = (void *)&exynosautov9_spi_port_config,
>  	},
Re: [PATCH 5/7] spi: s3c64xx: Add Exynos850 support
Posted by Sam Protsenko 1 year, 11 months ago 
On Wed, Jan 24, 2024 at 12:49 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>
>
>
> On 1/20/24 01:29, Sam Protsenko wrote:
> > Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
> > can be configured in SPI mode:
> >
> >   * spi_0: BLK_PERI_SPI_0 (0x13940000)
> >   * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
> >   * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)
> >
> > SPI FIFO depth is 64 bytes for all those SPI blocks, so the
> > .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
> > default internal clock divider, and an internal loopback mode to run
> > a loopback test.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
>
> > ---
> >  drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> > index 0e48ffd499b9..f7d623ad6ac3 100644
> > --- a/drivers/spi/spi-s3c64xx.c
> > +++ b/drivers/spi/spi-s3c64xx.c
> > @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
> >       .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
> >  };
> >
> > +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
> > +     .fifo_lvl_mask  = { 0x7f, 0x7f, 0x7f },
>
> I'll come with a follow up patch on top of this. Having the dt alias
> used as an index in the fifo_lvl_mask to determine the FIFO depth is
> wrong. Not only because of the dependency on the alias, but also because
> the fifo_lvl_mask value does not reflect the FIFO level reg field.
> Playing with what we have now is ok by me, I find the patch good.
>

Yeah, we just have to make sure all our patches are taken in the
correct order, to avoid any possible conflicts.

> > +     .rx_lvl_offset  = 15,
> > +     .tx_st_done     = 25,
> > +     .clk_div        = 4,
> > +     .high_speed     = true,
> > +     .clk_from_cmu   = true,
> > +     .has_loopback   = true,
> > +     .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
> > +};
> > +
> >  static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
> >       .fifo_lvl_mask  = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
> >                           0x7f, 0x7f, 0x7f, 0x7f},
> > @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
> >       { .compatible = "samsung,exynos5433-spi",
> >                       .data = (void *)&exynos5433_spi_port_config,
> >       },
> > +     { .compatible = "samsung,exynos850-spi",
> > +                     .data = (void *)&exynos850_spi_port_config,
> > +     },
> >       { .compatible = "samsung,exynosautov9-spi",
> >                       .data = (void *)&exynosautov9_spi_port_config,
> >       },

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