From: Elad Nachman <enachman@marvell.com>

This patch series adds support for the Marvell AC5/X/IM series of SOCs.
The main hurdles in supporting these SOCs are the following limitations:
1. DDR starts at offset 0x2_0000_0000
2. mmc controller has only 31-bit path on the crossbar to the DDR.

Point number one is solved by the first patch, which targets the
arm64 subsystem, by taking into account the DDR start address when
calculating the DMA and DMA32 zones.

This yields the correct split between DMA, DMA32 and NORMAL zones
according to the device tree CPU address limitations.

Point number two is solved in the mmc xenon driver by detecting the memory
size, and when it is more than 2GB, disable ADMA and 64-bit DMA, which
effectively enables SDMA with a bounce buffer.
DMA mask is then set manually to 34 bit to account for the DDR starting
at offset 0x2_0000_0000 .

Elad Nachman (4):
  arm64: mm: Fix SOCs with DDR starting above zero
  dt-bindings: mmc: add Marvell ac5
  arm64: dts: ac5: add mmc node and clock
  mmc: xenon: Add ac5 support via bounce buffer

 .../bindings/mmc/marvell,xenon-sdhci.yaml     |  3 ++
 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 33 ++++++++++++++++++-
 arch/arm64/mm/init.c                          | 20 ++++++++---
 drivers/mmc/host/sdhci-xenon.c                | 33 ++++++++++++++++++-
 drivers/mmc/host/sdhci-xenon.h                |  3 +-
 5 files changed, 84 insertions(+), 8 deletions(-)

-- 
2.25.1

On Wed, Dec 27, 2023 at 02:32:53PM +0200, Elad Nachman wrote:
> From: Elad Nachman <enachman@marvell.com>
> 
> This patch series adds support for the Marvell AC5/X/IM series of SOCs.
> The main hurdles in supporting these SOCs are the following limitations:
> 1. DDR starts at offset 0x2_0000_0000
> 2. mmc controller has only 31-bit path on the crossbar to the DDR.
> 
> Point number one is solved by the first patch, which targets the
> arm64 subsystem, by taking into account the DDR start address when
> calculating the DMA and DMA32 zones.
> 
> This yields the correct split between DMA, DMA32 and NORMAL zones
> according to the device tree CPU address limitations.
> 
> Point number two is solved in the mmc xenon driver by detecting the memory
> size, and when it is more than 2GB, disable ADMA and 64-bit DMA, which
> effectively enables SDMA with a bounce buffer.
> DMA mask is then set manually to 34 bit to account for the DDR starting
> at offset 0x2_0000_0000 .

You probably need to split this patchset up since the first patch will
get merged via the arm64 core maintainers, the MMC driver change via
the MMC maintainers, and maybe the DT changes for the
ac5-98dx25xx.dtsi via the mvebu maintainers, or the MMC maintainer?

	Andrew