Add a driver for the Marvell 88Q2220. This driver allows to detect the
link, switch between 100BASE-T1 and 1000BASE-T1 and switch between
master and slave mode and autonegotiation.
Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com>
---
drivers/net/phy/marvell-88q2xxx.c | 310 ++++++++++++++++++++++++++++--
include/linux/marvell_phy.h | 1 +
2 files changed, 300 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/marvell-88q2xxx.c b/drivers/net/phy/marvell-88q2xxx.c
index 1c3ff77de56b..4e930b5ffaef 100644
--- a/drivers/net/phy/marvell-88q2xxx.c
+++ b/drivers/net/phy/marvell-88q2xxx.c
@@ -27,6 +27,13 @@
#define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK 0x0004
#define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE 0x0008
+#define MDIO_MMD_PCS_MV_RX_STAT 33328
+
+#define MDIO_MMD_AN_MV_STAT2 32794
+#define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
+#define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
+#define MDIO_MMD_AN_MV_STAT2_1000BT1 0x4000
+
static int mv88q2xxx_soft_reset(struct phy_device *phydev)
{
int ret;
@@ -120,24 +127,87 @@ static int mv88q2xxx_read_link_100m(struct phy_device *phydev)
static int mv88q2xxx_read_link(struct phy_device *phydev)
{
- int ret;
-
/* The 88Q2XXX PHYs do not have the PMA/PMD status register available,
* therefore we need to read the link status from the vendor specific
* registers depending on the speed.
*/
+
if (phydev->speed == SPEED_1000)
- ret = mv88q2xxx_read_link_gbit(phydev);
+ return mv88q2xxx_read_link_gbit(phydev);
+ else if (phydev->speed == SPEED_100)
+ return mv88q2xxx_read_link_100m(phydev);
+
+ phydev->link = false;
+ return 0;
+}
+
+static int mv88q2xxx_read_master_slave_state(struct phy_device *phydev)
+{
+ int ret;
+
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT);
+ if (ret < 0)
+ return ret;
+
+ if (ret & MDIO_MMD_AN_MV_STAT_LOCAL_MASTER)
+ phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
else
- ret = mv88q2xxx_read_link_100m(phydev);
+ phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
+
+ return 0;
+}
+
+static int mv88q2xxx_read_aneg_speed(struct phy_device *phydev)
+{
+ int ret;
- return ret;
+ phydev->speed = SPEED_UNKNOWN;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT2);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & MDIO_MMD_AN_MV_STAT2_AN_RESOLVED))
+ return 0;
+
+ if (ret & MDIO_MMD_AN_MV_STAT2_100BT1)
+ phydev->speed = SPEED_100;
+ else if (ret & MDIO_MMD_AN_MV_STAT2_1000BT1)
+ phydev->speed = SPEED_1000;
+
+ return 0;
}
static int mv88q2xxx_read_status(struct phy_device *phydev)
{
int ret;
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ phydev->duplex = DUPLEX_FULL;
+
+ /* We have to get the negotiated speed first, otherwise we are
+ * not able to read the link.
+ */
+ ret = mv88q2xxx_read_aneg_speed(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = mv88q2xxx_read_link(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = genphy_c45_read_lpa(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = genphy_c45_baset1_read_status(phydev);
+ if (ret < 0)
+ return ret;
+
+ return mv88q2xxx_read_master_slave_state(phydev);
+ }
+
ret = mv88q2xxx_read_link(phydev);
if (ret < 0)
return ret;
@@ -166,7 +236,9 @@ static int mv88q2xxx_get_features(struct phy_device *phydev)
* sequence provided by Marvell. Disable it for now until a proper
* workaround is found or a new PHY revision is released.
*/
- linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+ if (phydev->drv->phy_id == MARVELL_PHY_ID_88Q2110)
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
return 0;
}
@@ -192,6 +264,9 @@ static int mv88q2xxx_config_init(struct phy_device *phydev)
*/
phydev->pma_extable = MDIO_PMA_EXTABLE_BT1;
+ if (phydev->drv->phy_id == MARVELL_PHY_ID_88Q2220)
+ return 0;
+
/* Read the current PHY configuration */
ret = genphy_c45_read_pma(phydev);
if (ret)
@@ -200,7 +275,7 @@ static int mv88q2xxx_config_init(struct phy_device *phydev)
return mv88q2xxx_config_aneg(phydev);
}
-static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
+static int mv88q2xxx_get_sqi(struct phy_device *phydev)
{
int ret;
@@ -208,7 +283,8 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
/* Read the SQI from the vendor specific receiver status
* register
*/
- ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8230);
+ ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
+ MDIO_MMD_PCS_MV_RX_STAT);
if (ret < 0)
return ret;
@@ -230,11 +306,208 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
return ret & 0x0F;
}
-static int mv88q2xxxx_get_sqi_max(struct phy_device *phydev)
+static int mv88q2xxx_get_sqi_max(struct phy_device *phydev)
{
return 15;
}
+static int mv88q222x_soft_reset(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Enable RESET of DCL */
+ if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) {
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Soft reset */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_CTRL,
+ MDIO_PCS_1000BT1_CTRL_RESET);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc);
+ if (ret < 0)
+ return ret;
+
+ /* Disable RESET of DCL */
+ if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000)
+ return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58);
+ else
+ return ret;
+}
+
+static int mv88q222x_config_aneg_gbit(struct phy_device *phydev)
+{
+ int ret;
+
+ /* send_s detection threshold, slave and master */
+ ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8032, 0x2020);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8031, 0xa28);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_AN, 0x8031, 0xc28);
+ if (ret < 0)
+ return ret;
+
+ /* Disable DCL calibratin during tear down */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffdb, 0xfc10);
+ if (ret < 0)
+ return ret;
+
+ /* Disable RESET of DCL*/
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58);
+ if (ret < 0)
+ return ret;
+
+ /* Turn CM Clamp ON */
+ return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe79, 0x4);
+}
+
+static int mv88q222x_config_aneg_100m(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Update Initial FFE Coefficients */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfbba, 0xcb2);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfbbb, 0xc4a);
+ if (ret < 0)
+ return ret;
+
+ /* Turn CM Clamp ON */
+ return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe79, 0x4);
+}
+
+static int mv88q222x_config_aneg_preinit(struct phy_device *phydev)
+{
+ int ret, val, i;
+
+ /* Enable txdac */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8033, 0x6801);
+ if (ret < 0)
+ return ret;
+
+ /* Disable ANEG */
+ ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0);
+ if (ret < 0)
+ return ret;
+
+ /* Set IEEE power down */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
+ MDIO_CTRL1_LPOWER | MDIO_PMA_CTRL1_SPEED1000);
+ if (ret < 0)
+ return ret;
+
+ /* Exit standby state(internal state) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48);
+ if (ret < 0)
+ return ret;
+
+ /* Set power management state breakpoint (internal state) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0x6b6);
+ if (ret < 0)
+ return ret;
+
+ /* Exit IEEE power down */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 0x0);
+ if (ret < 0)
+ return ret;
+
+ /* Wait up to 5ms to enter to power management state, if we do not meet
+ * the target value, it is still ok to proceed
+ */
+ for (i = 0; i < 5; i++) {
+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, 0xffe4);
+ if (val == 0x6ba)
+ break;
+
+ usleep_range(1000, 2000);
+ }
+
+ /* Turn CM Clamp OFF */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe79, 0x0);
+ if (ret < 0)
+ return ret;
+
+ /* mdi vcm */
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe07, 0x125a);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe09, 0x1288);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe08, 0x2588);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe11, 0x1105);
+ if (ret < 0)
+ return ret;
+
+ /* aux_boost */
+ return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe72, 0x042c);
+}
+
+static int mv88q222x_config_aneg_init_b0(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = mv88q222x_config_aneg_preinit(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->autoneg == AUTONEG_DISABLE) {
+ if (phydev->speed == SPEED_100)
+ return mv88q222x_config_aneg_100m(phydev);
+ else
+ return mv88q222x_config_aneg_gbit(phydev);
+ }
+
+ ret = mv88q222x_config_aneg_100m(phydev);
+ if (ret)
+ return ret;
+
+ ret = mv88q222x_config_aneg_gbit(phydev);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe5f, 0xe8);
+ if (ret)
+ return ret;
+
+ return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe05, 0x755c);
+}
+
+static int mv88q222x_config_aneg(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = mv88q222x_config_aneg_init_b0(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = genphy_c45_config_aneg(phydev);
+ if (ret)
+ return ret;
+
+ return mv88q222x_soft_reset(phydev);
+}
+
static struct phy_driver mv88q2xxx_driver[] = {
{
.phy_id = MARVELL_PHY_ID_88Q2110,
@@ -246,8 +519,22 @@ static struct phy_driver mv88q2xxx_driver[] = {
.read_status = mv88q2xxx_read_status,
.soft_reset = mv88q2xxx_soft_reset,
.set_loopback = genphy_c45_loopback,
- .get_sqi = mv88q2xxxx_get_sqi,
- .get_sqi_max = mv88q2xxxx_get_sqi_max,
+ .get_sqi = mv88q2xxx_get_sqi,
+ .get_sqi_max = mv88q2xxx_get_sqi_max,
+ },
+ {
+ .phy_id = MARVELL_PHY_ID_88Q2220,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "mv88q2220",
+ .get_features = mv88q2xxx_get_features,
+ .config_aneg = mv88q222x_config_aneg,
+ .aneg_done = genphy_c45_aneg_done,
+ .config_init = mv88q2xxx_config_init,
+ .read_status = mv88q2xxx_read_status,
+ .soft_reset = mv88q222x_soft_reset,
+ .set_loopback = genphy_c45_loopback,
+ .get_sqi = mv88q2xxx_get_sqi,
+ .get_sqi_max = mv88q2xxx_get_sqi_max,
},
};
@@ -255,6 +542,7 @@ module_phy_driver(mv88q2xxx_driver);
static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = {
{ MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88Q2220, MARVELL_PHY_ID_MASK },
{ /*sentinel*/ }
};
MODULE_DEVICE_TABLE(mdio, mv88q2xxx_tbl);
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index 9b54c4f0677f..693eba9869e4 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -26,6 +26,7 @@
#define MARVELL_PHY_ID_88E2110 0x002b09b0
#define MARVELL_PHY_ID_88X2222 0x01410f10
#define MARVELL_PHY_ID_88Q2110 0x002b0980
+#define MARVELL_PHY_ID_88Q2220 0x002b0b20
/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
#define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0
--
2.39.2Hi Dimitri, On Thu, Dec 21, 2023 at 08:28:51AM +0100, Dimitri Fedrau wrote: > Add a driver for the Marvell 88Q2220. This driver allows to detect the > link, switch between 100BASE-T1 and 1000BASE-T1 and switch between > master and slave mode and autonegotiation. > > Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> I tried to make your patch work in my setup but I'm unable to force a link speed. Were you able to force a different link speed with the following command? ethtool -s eth0 speed 100 autoneg off Regards, Stefan
Am Thu, Dec 21, 2023 at 02:47:57PM +0100 schrieb Stefan Eichenberger: > Hi Dimitri, > Hi Stefan, > On Thu, Dec 21, 2023 at 08:28:51AM +0100, Dimitri Fedrau wrote: > > Add a driver for the Marvell 88Q2220. This driver allows to detect the > > link, switch between 100BASE-T1 and 1000BASE-T1 and switch between > > master and slave mode and autonegotiation. > > > > Signed-off-by: Dimitri Fedrau <dima.fedrau@gmail.com> > > I tried to make your patch work in my setup but I'm unable to force a > link speed. Were you able to force a different link speed with the > following command? > ethtool -s eth0 speed 100 autoneg off > I tested following modes, which all worked: ethtool -s eth0 autoneg on master-slave forced-master ethtool -s eth0 autoneg on master-slave preferred-master ethtool -s eth0 autoneg on master-slave preferred-slave ethtool -s eth0 autoneg on master-slave forced-slave ethtool -s eth0 autoneg on master-slave forced-master speed 100 ethtool -s eth0 autoneg on master-slave preferred-master speed 100 ethtool -s eth0 autoneg on master-slave preferred-slave speed 100 ethtool -s eth0 autoneg on master-slave forced-slave speed 100 ethtool -s eth0 autoneg off master-slave forced-master speed 1000 ethtool -s eth0 autoneg off master-slave preferred-master speed 1000 ethtool -s eth0 autoneg off master-slave preferred-slave speed 1000 ethtool -s eth0 autoneg off master-slave forced-slave speed 1000 ethtool -s eth0 autoneg off master-slave forced-master speed 100 ethtool -s eth0 autoneg off master-slave preferred-master speed 100 ethtool -s eth0 autoneg off master-slave preferred-slave speed 100 ethtool -s eth0 autoneg off master-slave forced-slave speed 100 Without setting the master-slave option it didn't work. I think its mandatory. > Regards, > Stefan Best regards, Stefan
> Without setting the master-slave option it didn't work. I think its
> mandatory.
I don't think it is. The PHY should have a default setting for
master-slave. Often its based on the typical use case. If its
typically inside a switch, then it should default to prefer-master. If
its typically in an end system, then it should be prefer-slave.
Andrew
On Thu, Dec 21, 2023 at 03:25:56PM +0100, Andrew Lunn wrote: > > Without setting the master-slave option it didn't work. I think its > > mandatory. > > I don't think it is. The PHY should have a default setting for > master-slave. Often its based on the typical use case. If its > typically inside a switch, then it should default to prefer-master. If > its typically in an end system, then it should be prefer-slave. However, master/slave needs autoneg, and if autoneg is disabled, then that may not be resolvable, and it may need manual configuration. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Am Thu, Dec 21, 2023 at 03:25:56PM +0100 schrieb Andrew Lunn:
> > Without setting the master-slave option it didn't work. I think its
> > mandatory.
>
> I don't think it is. The PHY should have a default setting for
> master-slave. Often its based on the typical use case. If its
> typically inside a switch, then it should default to prefer-master. If
> its typically in an end system, then it should be prefer-slave.
>
That would be the case if you use a forced configuration. I think this
is already implemented by reading out the MDIO_PMA_PMD_BT1_CTRL in
genphy_c45_pma_baset1_read_master_slave. Probably the problem arises
with following lines which prevents an inital read of the configuration:
static int mv88q2xxx_config_init(struct phy_device *phydev)
{
int ret;
/* The 88Q2XXX PHYs do have the extended ability register available, but
* register MDIO_PMA_EXTABLE where they should signalize it does not
* work according to specification. Therefore, we force it here.
*/
phydev->pma_extable = MDIO_PMA_EXTABLE_BT1;
if (phydev->drv->phy_id == MARVELL_PHY_ID_88Q2220)
return 0;
/* Read the current PHY configuration */
ret = genphy_c45_read_pma(phydev);
if (ret)
return ret;
return mv88q2xxx_config_aneg(phydev);
}
If I type in "ethtool -s eth0 autoneg on" I don't have to set the
master-slave option. Is the assumption here that we always start with a
forced configuration ? If yes, then I have to fix it.
> Andrew
Dimitri
> -static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> +static int mv88q2xxx_get_sqi(struct phy_device *phydev)
> {
> int ret;
>
> @@ -208,7 +283,8 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> /* Read the SQI from the vendor specific receiver status
> * register
> */
> - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8230);
> + ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
> + MDIO_MMD_PCS_MV_RX_STAT);
> if (ret < 0)
> return ret;
>
> @@ -230,11 +306,208 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> return ret & 0x0F;
> }
>
> -static int mv88q2xxxx_get_sqi_max(struct phy_device *phydev)
> +static int mv88q2xxx_get_sqi_max(struct phy_device *phydev)
> {
> return 15;
> }
This could be a patch of its own.
Andrew
Am Thu, Dec 21, 2023 at 10:53:27AM +0100 schrieb Andrew Lunn:
> > -static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> > +static int mv88q2xxx_get_sqi(struct phy_device *phydev)
> > {
> > int ret;
> >
> > @@ -208,7 +283,8 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> > /* Read the SQI from the vendor specific receiver status
> > * register
> > */
> > - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8230);
> > + ret = phy_read_mmd(phydev, MDIO_MMD_PCS,
> > + MDIO_MMD_PCS_MV_RX_STAT);
> > if (ret < 0)
> > return ret;
> >
> > @@ -230,11 +306,208 @@ static int mv88q2xxxx_get_sqi(struct phy_device *phydev)
> > return ret & 0x0F;
> > }
> >
> > -static int mv88q2xxxx_get_sqi_max(struct phy_device *phydev)
> > +static int mv88q2xxx_get_sqi_max(struct phy_device *phydev)
> > {
> > return 15;
> > }
>
> This could be a patch of its own.
>
Will fix this in V4.
> Andrew
Best regards,
Dimitri
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