On 12/22/2023 3:09 AM, Andrew Halaney wrote:
> Currently, the reset bit for the UFS provided reset controller (used by
> its phy) is written to, and then a mb() happens to try and ensure that
> hit the device. Immediately afterwards a usleep_range() occurs.
>
> mb() ensure that the write completes, but completion doesn't mean that
> it isn't stored in a buffer somewhere. The recommendation for
> ensuring this bit has taken effect on the device is to perform a read
> back to force it to make it all the way to the device. This is
> documented in device-io.rst and a talk by Will Deacon on this can
> be seen over here:
>
> https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678
>
> Let's do that to ensure the bit hits the device. By doing so and
> guaranteeing the ordering against the immediately following
> usleep_range(), the mb() can safely be removed.
>
> Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms")
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
> ---
> drivers/ufs/host/ufs-qcom.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 9dd9a391ebb7..b9de170983c9 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -151,10 +151,10 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
> ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
>
> /*
> - * Make sure assertion of ufs phy reset is written to
> - * register before returning
> + * Dummy read to ensure the write takes effect before doing any sort
> + * of delay
> */
> - mb();
> + ufshcd_readl(hba, REG_UFS_CFG1);
> }
>
> static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
> @@ -162,10 +162,10 @@ static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
> ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);
>
> /*
> - * Make sure de-assertion of ufs phy reset is written to
> - * register before returning
> + * Dummy read to ensure the write takes effect before doing any sort
> + * of delay
> */
> - mb();
> + ufshcd_readl(hba, REG_UFS_CFG1);
> }
>
> /* Host controller hardware version: major.minor.step */
>
Reviewed-by: Can Guo <quic_cang@quicinc.com>