Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located.
To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as private data.
Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node.
e.g.,
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
...
cpu0-intc: interrupt-controller {
#interrupt-cells = <0x01>;
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Return -ENXIO if no valid compatible INTC found
- Allow falling back to generic RISC-V INTC
Changes v3 -> v4: (Suggested by Thomas [1])
- Add comment to andes irq chip function
- Refine code flow to share with generic RISC-V INTC and ACPI
- Move Andes specific definitions to include/linux/soc/andes/irq.h
Changes v4 -> v5: (Suggested by Thomas)
- Fix commit message
- Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
- Do not set chip_data to the chip itself with irq_domain_set_info()
- Follow reverse fir tree order variable declarations
[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
---
drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++----
include/linux/soc/andes/irq.h | 17 ++++++++++
2 files changed, 64 insertions(+), 6 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 2fdd40f2a791..0b6bf3fb1dba 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
static struct irq_domain *intc_domain;
@@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+ /*
+ * Andes specific S-mode local interrupt causes (hwirq)
+ * are defined as (256 + n) and controlled by n-th bit
+ * of SLIE.
+ */
+ unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_clear(CSR_IE, mask);
+ else
+ csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_set(CSR_IE, mask);
+ else
+ csr_set(ANDES_CSR_SLIE, mask);
+}
+
static void riscv_intc_irq_eoi(struct irq_data *d)
{
/*
@@ -69,11 +95,20 @@ static struct irq_chip riscv_intc_chip = {
.irq_eoi = riscv_intc_irq_eoi,
};
+static struct irq_chip andes_intc_chip = {
+ .name = "RISC-V INTC",
+ .irq_mask = andes_intc_irq_mask,
+ .irq_unmask = andes_intc_irq_unmask,
+ .irq_eoi = riscv_intc_irq_eoi,
+};
+
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
+ struct irq_chip *chip = d->host_data;
+
irq_set_percpu_devid(irq);
- irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
+ irq_domain_set_info(d, irq, hwirq, chip, NULL,
handle_percpu_devid_irq, NULL, NULL);
return 0;
@@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
return intc_domain->fwnode;
}
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+ struct irq_chip *chip)
{
int rc;
- intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -136,8 +172,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
- int rc;
+ struct irq_chip *chip = &riscv_intc_chip;
unsigned long hartid;
+ int rc;
rc = riscv_of_parent_hartid(node, &hartid);
if (rc < 0) {
@@ -162,10 +199,14 @@ static int __init riscv_intc_init(struct device_node *node,
return 0;
}
- return riscv_intc_init_common(of_node_to_fwnode(node));
+ if (of_device_is_compatible(node, "andestech,cpu-intc"))
+ chip = &andes_intc_chip;
+
+ return riscv_intc_init_common(of_node_to_fwnode(node), chip);
}
IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
#ifdef CONFIG_ACPI
@@ -192,7 +233,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
return -ENOMEM;
}
- return riscv_intc_init_common(fn);
+ return riscv_intc_init_common(fn, &riscv_intc_chip);
}
IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..f03e68fea261
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMU 18
+#define ANDES_SLI_CAUSE_BASE 256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE 0x9c4
+#define ANDES_CSR_SLIP 0x9c5
+#define ANDES_CSR_SCOUNTEROF 0x9d4
+
+#endif /* __ANDES_IRQ_H */
--
2.34.1On Wed, Dec 13, 2023 at 12:35 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node.
> e.g.,
>
> cpu0: cpu@0 {
> compatible = "andestech,ax45mp", "riscv";
> ...
> cpu0-intc: interrupt-controller {
> #interrupt-cells = <0x01>;
> compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> interrupt-controller;
> };
> };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Return -ENXIO if no valid compatible INTC found
> - Allow falling back to generic RISC-V INTC
> Changes v3 -> v4: (Suggested by Thomas [1])
> - Add comment to andes irq chip function
> - Refine code flow to share with generic RISC-V INTC and ACPI
> - Move Andes specific definitions to include/linux/soc/andes/irq.h
> Changes v4 -> v5: (Suggested by Thomas)
> - Fix commit message
> - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
> - Do not set chip_data to the chip itself with irq_domain_set_info()
> - Follow reverse fir tree order variable declarations
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> ---
> drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++----
> include/linux/soc/andes/irq.h | 17 ++++++++++
> 2 files changed, 64 insertions(+), 6 deletions(-)
> create mode 100644 include/linux/soc/andes/irq.h
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index 2fdd40f2a791..0b6bf3fb1dba 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -17,6 +17,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/smp.h>
> +#include <linux/soc/andes/irq.h>
>
> static struct irq_domain *intc_domain;
>
> @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> csr_set(CSR_IE, BIT(d->hwirq));
> }
>
> +static void andes_intc_irq_mask(struct irq_data *d)
> +{
> + /*
> + * Andes specific S-mode local interrupt causes (hwirq)
> + * are defined as (256 + n) and controlled by n-th bit
> + * of SLIE.
> + */
> + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> +
> + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> + csr_clear(CSR_IE, mask);
> + else
> + csr_clear(ANDES_CSR_SLIE, mask);
> +}
> +
> +static void andes_intc_irq_unmask(struct irq_data *d)
> +{
> + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> +
> + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> + csr_set(CSR_IE, mask);
> + else
> + csr_set(ANDES_CSR_SLIE, mask);
Clearly, Andes does not have any CSR for:
XLEN <= local interrupt <ANDES_SLI_CAUSE_BASE
and
ANDES_SLI_CAUSE_BASE + XLEN <= local interrupt
Regards,
Anup
> +}
> +
> static void riscv_intc_irq_eoi(struct irq_data *d)
> {
> /*
> @@ -69,11 +95,20 @@ static struct irq_chip riscv_intc_chip = {
> .irq_eoi = riscv_intc_irq_eoi,
> };
>
> +static struct irq_chip andes_intc_chip = {
> + .name = "RISC-V INTC",
> + .irq_mask = andes_intc_irq_mask,
> + .irq_unmask = andes_intc_irq_unmask,
> + .irq_eoi = riscv_intc_irq_eoi,
> +};
> +
> static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
> irq_hw_number_t hwirq)
> {
> + struct irq_chip *chip = d->host_data;
> +
> irq_set_percpu_devid(irq);
> - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> + irq_domain_set_info(d, irq, hwirq, chip, NULL,
> handle_percpu_devid_irq, NULL, NULL);
>
> return 0;
> @@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
> return intc_domain->fwnode;
> }
>
> -static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> +static int __init riscv_intc_init_common(struct fwnode_handle *fn,
> + struct irq_chip *chip)
> {
> int rc;
>
> - intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
> if (!intc_domain) {
> pr_err("unable to add IRQ domain\n");
> return -ENXIO;
> @@ -136,8 +172,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> static int __init riscv_intc_init(struct device_node *node,
> struct device_node *parent)
> {
> - int rc;
> + struct irq_chip *chip = &riscv_intc_chip;
> unsigned long hartid;
> + int rc;
>
> rc = riscv_of_parent_hartid(node, &hartid);
> if (rc < 0) {
> @@ -162,10 +199,14 @@ static int __init riscv_intc_init(struct device_node *node,
> return 0;
> }
>
> - return riscv_intc_init_common(of_node_to_fwnode(node));
> + if (of_device_is_compatible(node, "andestech,cpu-intc"))
> + chip = &andes_intc_chip;
> +
> + return riscv_intc_init_common(of_node_to_fwnode(node), chip);
> }
>
> IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
> +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
>
> #ifdef CONFIG_ACPI
>
> @@ -192,7 +233,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
> return -ENOMEM;
> }
>
> - return riscv_intc_init_common(fn);
> + return riscv_intc_init_common(fn, &riscv_intc_chip);
> }
>
> IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
> diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
> new file mode 100644
> index 000000000000..f03e68fea261
> --- /dev/null
> +++ b/include/linux/soc/andes/irq.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2023 Andes Technology Corporation
> + */
> +#ifndef __ANDES_IRQ_H
> +#define __ANDES_IRQ_H
> +
> +/* Andes PMU irq number */
> +#define ANDES_RV_IRQ_PMU 18
> +#define ANDES_SLI_CAUSE_BASE 256
> +
> +/* Andes PMU related registers */
> +#define ANDES_CSR_SLIE 0x9c4
> +#define ANDES_CSR_SLIP 0x9c5
> +#define ANDES_CSR_SCOUNTEROF 0x9d4
> +
> +#endif /* __ANDES_IRQ_H */
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Dec 13, 2023 at 08:15:28PM +0530, Anup Patel wrote:
> On Wed, Dec 13, 2023 at 12:35 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add support for the Andes hart-level interrupt controller. This
> > controller provides interrupt mask/unmask functions to access the
> > custom register (SLIE) where the non-standard S-mode local interrupt
> > enable bits are located.
> >
> > To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> > ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> > passed to the irq_domain_set_info() as private data.
> >
> > Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> > compatible string to be present in interrupt-controller of cpu node.
> > e.g.,
> >
> > cpu0: cpu@0 {
> > compatible = "andestech,ax45mp", "riscv";
> > ...
> > cpu0-intc: interrupt-controller {
> > #interrupt-cells = <0x01>;
> > compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> > interrupt-controller;
> > };
> > };
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > Changes v2 -> v3:
> > - Return -ENXIO if no valid compatible INTC found
> > - Allow falling back to generic RISC-V INTC
> > Changes v3 -> v4: (Suggested by Thomas [1])
> > - Add comment to andes irq chip function
> > - Refine code flow to share with generic RISC-V INTC and ACPI
> > - Move Andes specific definitions to include/linux/soc/andes/irq.h
> > Changes v4 -> v5: (Suggested by Thomas)
> > - Fix commit message
> > - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
> > - Do not set chip_data to the chip itself with irq_domain_set_info()
> > - Follow reverse fir tree order variable declarations
> >
> > [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> > ---
> > drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++----
> > include/linux/soc/andes/irq.h | 17 ++++++++++
> > 2 files changed, 64 insertions(+), 6 deletions(-)
> > create mode 100644 include/linux/soc/andes/irq.h
> >
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index 2fdd40f2a791..0b6bf3fb1dba 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -17,6 +17,7 @@
> > #include <linux/module.h>
> > #include <linux/of.h>
> > #include <linux/smp.h>
> > +#include <linux/soc/andes/irq.h>
> >
> > static struct irq_domain *intc_domain;
> >
> > @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> > csr_set(CSR_IE, BIT(d->hwirq));
> > }
> >
> > +static void andes_intc_irq_mask(struct irq_data *d)
> > +{
> > + /*
> > + * Andes specific S-mode local interrupt causes (hwirq)
> > + * are defined as (256 + n) and controlled by n-th bit
> > + * of SLIE.
> > + */
> > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > +
> > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > + csr_clear(CSR_IE, mask);
> > + else
> > + csr_clear(ANDES_CSR_SLIE, mask);
> > +}
> > +
> > +static void andes_intc_irq_unmask(struct irq_data *d)
> > +{
> > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > +
> > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > + csr_set(CSR_IE, mask);
> > + else
> > + csr_set(ANDES_CSR_SLIE, mask);
>
> Clearly, Andes does not have any CSR for:
> XLEN <= local interrupt <ANDES_SLI_CAUSE_BASE
> and
> ANDES_SLI_CAUSE_BASE + XLEN <= local interrupt
Ah, what am I doing here.
sorry for that silly patch.
Regards,
Peter Lin
> Regards,
> Anup
On Wed, Dec 13, 2023 at 9:15 PM Yu-Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> On Wed, Dec 13, 2023 at 08:15:28PM +0530, Anup Patel wrote:
> > On Wed, Dec 13, 2023 at 12:35 PM Yu Chien Peter Lin
> > <peterlin@andestech.com> wrote:
> > >
> > > Add support for the Andes hart-level interrupt controller. This
> > > controller provides interrupt mask/unmask functions to access the
> > > custom register (SLIE) where the non-standard S-mode local interrupt
> > > enable bits are located.
> > >
> > > To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> > > ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> > > passed to the irq_domain_set_info() as private data.
> > >
> > > Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> > > compatible string to be present in interrupt-controller of cpu node.
> > > e.g.,
> > >
> > > cpu0: cpu@0 {
> > > compatible = "andestech,ax45mp", "riscv";
> > > ...
> > > cpu0-intc: interrupt-controller {
> > > #interrupt-cells = <0x01>;
> > > compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> > > interrupt-controller;
> > > };
> > > };
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> > > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > > ---
> > > Changes v1 -> v2:
> > > - New patch
> > > Changes v2 -> v3:
> > > - Return -ENXIO if no valid compatible INTC found
> > > - Allow falling back to generic RISC-V INTC
> > > Changes v3 -> v4: (Suggested by Thomas [1])
> > > - Add comment to andes irq chip function
> > > - Refine code flow to share with generic RISC-V INTC and ACPI
> > > - Move Andes specific definitions to include/linux/soc/andes/irq.h
> > > Changes v4 -> v5: (Suggested by Thomas)
> > > - Fix commit message
> > > - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
> > > - Do not set chip_data to the chip itself with irq_domain_set_info()
> > > - Follow reverse fir tree order variable declarations
> > >
> > > [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> > > ---
> > > drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++----
> > > include/linux/soc/andes/irq.h | 17 ++++++++++
> > > 2 files changed, 64 insertions(+), 6 deletions(-)
> > > create mode 100644 include/linux/soc/andes/irq.h
> > >
> > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > > index 2fdd40f2a791..0b6bf3fb1dba 100644
> > > --- a/drivers/irqchip/irq-riscv-intc.c
> > > +++ b/drivers/irqchip/irq-riscv-intc.c
> > > @@ -17,6 +17,7 @@
> > > #include <linux/module.h>
> > > #include <linux/of.h>
> > > #include <linux/smp.h>
> > > +#include <linux/soc/andes/irq.h>
> > >
> > > static struct irq_domain *intc_domain;
> > >
> > > @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> > > csr_set(CSR_IE, BIT(d->hwirq));
> > > }
> > >
> > > +static void andes_intc_irq_mask(struct irq_data *d)
> > > +{
> > > + /*
> > > + * Andes specific S-mode local interrupt causes (hwirq)
> > > + * are defined as (256 + n) and controlled by n-th bit
> > > + * of SLIE.
> > > + */
> > > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > > +
> > > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > > + csr_clear(CSR_IE, mask);
> > > + else
> > > + csr_clear(ANDES_CSR_SLIE, mask);
> > > +}
> > > +
> > > +static void andes_intc_irq_unmask(struct irq_data *d)
> > > +{
> > > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > > +
> > > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > > + csr_set(CSR_IE, mask);
> > > + else
> > > + csr_set(ANDES_CSR_SLIE, mask);
> >
> > Clearly, Andes does not have any CSR for:
> > XLEN <= local interrupt <ANDES_SLI_CAUSE_BASE
> > and
> > ANDES_SLI_CAUSE_BASE + XLEN <= local interrupt
>
> Ah, what am I doing here.
> sorry for that silly patch.
This patch is okay only if we can guarantee that
hwirq is within accepted range.
For example, riscv_intc_domain_alloc() can deny
invalid local interrupts.
Regards,
Anup
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