[PATCH v4 0/4] x86/cacheinfo: Set the number of leaves per CPU

Ricardo Neri posted 4 patches 2 years ago
There is a newer version of this series
arch/x86/kernel/cpu/cacheinfo.c | 49 +++++++++++++++++----------------
drivers/base/cacheinfo.c        |  9 +++++-
2 files changed, 34 insertions(+), 24 deletions(-)
[PATCH v4 0/4] x86/cacheinfo: Set the number of leaves per CPU
Posted by Ricardo Neri 2 years ago
Hi,

The interface /sys/devices/system/cpu/cpuX/cache is broken (not populated)
if CPUs have different numbers of subleaves in CPUID 4. This is the case
of Intel Meteor Lake.

This is v4 of a patchset to fix the cache sysfs interface by setting the
number of cache leaves independently for each CPU.

v1, v2, and v3 can be found here[1], here[2], and here[3].

All the tests described in [4] passed.

Changes since v3:
  * Fixed another NULL-pointer dereference when checking the validity of
    the last-level cache info.
  * Added the Reviewed-by tags from Radu and Sudeep. Thanks!
  * Rebased on v6.7-rc5.

Changes since v2:
  * This version uncovered a NULL-pointer dereference in recent changes to
    cacheinfo[5]. This dereference is observed when the system does not
    configure cacheinfo early during boot nor makes corrections later
    during CPU hotplug; as is the case in x86. Patch 1 fixes this issue.

Changes since v1:
  * Dave Hansen suggested to use the existing per-CPU ci_cpu_cacheinfo
    variable. Now the global variable num_cache_leaves became useless.
  * While here, I noticed that init_cache_level() also became useless:
    x86 does not need ci_cpu_cacheinfo::num_levels.

Thanks and BR,
Ricardo

[1]. https://lore.kernel.org/lkml/20230314231658.30169-1-ricardo.neri-calderon@linux.intel.com/
[2]. https://lore.kernel.org/all/20230424001956.21434-1-ricardo.neri-calderon@linux.intel.com/
[3]. https://lore.kernel.org/lkml/20230805012421.7002-1-ricardo.neri-calderon@linux.intel.com/
[4]. https://lore.kernel.org/lkml/20230912032350.GA17008@ranerica-svr.sc.intel.com/
[5]. https://lore.kernel.org/all/20230412185759.755408-1-rrendec@redhat.com/

Ricardo Neri (4):
  cacheinfo: Check for null last-level cache info
  cacheinfo: Allocate memory for memory if not done from the primary CPU
  x86/cacheinfo: Delete global num_cache_leaves
  x86/cacheinfo: Clean out init_cache_level()

 arch/x86/kernel/cpu/cacheinfo.c | 49 +++++++++++++++++----------------
 drivers/base/cacheinfo.c        |  9 +++++-
 2 files changed, 34 insertions(+), 24 deletions(-)

-- 
2.25.1
Re: [PATCH v4 0/4] x86/cacheinfo: Set the number of leaves per CPU
Posted by Ricardo Neri 1 year, 11 months ago
On Tue, Dec 12, 2023 at 02:25:15PM -0800, Ricardo Neri wrote:
> Hi,
> 
> The interface /sys/devices/system/cpu/cpuX/cache is broken (not populated)
> if CPUs have different numbers of subleaves in CPUID 4. This is the case
> of Intel Meteor Lake.

Hello. Wondering if there is any feedback on this patchset. The interface
/sys/devices/system/cpu/cpuX/cache is still broken on Meteor Lake with
v6.8-rc1.

I verified that this patchset applies cleanly on v6.8-rc1.

Thanks and BR,
Ricardo
Re: [PATCH v4 0/4] x86/cacheinfo: Set the number of leaves per CPU
Posted by Sudeep Holla 1 year, 11 months ago
On Wed, Jan 24, 2024 at 06:56:52PM -0800, Ricardo Neri wrote:
> On Tue, Dec 12, 2023 at 02:25:15PM -0800, Ricardo Neri wrote:
> > Hi,
> > 
> > The interface /sys/devices/system/cpu/cpuX/cache is broken (not populated)
> > if CPUs have different numbers of subleaves in CPUID 4. This is the case
> > of Intel Meteor Lake.
> 
> Hello. Wondering if there is any feedback on this patchset. The interface
> /sys/devices/system/cpu/cpuX/cache is still broken on Meteor Lake with
> v6.8-rc1.
> 
> I verified that this patchset applies cleanly on v6.8-rc1.
> 

Sorry I though I had acked it but now I see 1/4 is new in v4. I have
responded on the original patch.

--
Regards,
Sudeep