1. Patchew
  2. linux
  3. [PATCH v2 0/6] Initial device tree support for StarFive JH8100 SoC
  4. View patch

[PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC

Sia Jee Heng posted 6 patches 2 years, 1 month ago
There is a newer version of this series
[PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
Posted by Sia Jee Heng 2 years, 1 month ago 
Add device tree bindings for the StarFive JH8100 RISC-V SoC.

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index cc4d92f0a1bf..7e2da9eef3db 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -29,7 +29,10 @@ properties:
               - starfive,visionfive-2-v1.2a
               - starfive,visionfive-2-v1.3b
           - const: starfive,jh7110
-
+      - items:
+          - enum:
+              - starfive,jh8100-evb
+          - const: starfive,jh8100
 additionalProperties: true
 
 ...
-- 
2.34.1
Re: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
Posted by Conor Dooley 2 years ago 
On Wed, Nov 29, 2023 at 02:00:39PM +0800, Sia Jee Heng wrote:
> Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.
Re: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
Posted by Conor Dooley 2 years ago 
On Wed, Nov 29, 2023 at 02:46:26PM +0000, Conor Dooley wrote:
> On Wed, Nov 29, 2023 at 02:00:39PM +0800, Sia Jee Heng wrote:
> > Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> > 
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

(with the whitespace thing that Krzk pointed out fixed, just noticed
that)
Re: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
Posted by Krzysztof Kozlowski 2 years, 1 month ago 
On 29/11/2023 07:00, Sia Jee Heng wrote:
> Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index cc4d92f0a1bf..7e2da9eef3db 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -29,7 +29,10 @@ properties:
>                - starfive,visionfive-2-v1.2a
>                - starfive,visionfive-2-v1.3b
>            - const: starfive,jh7110
> -
> +      - items:
> +          - enum:
> +              - starfive,jh8100-evb
> +          - const: starfive,jh8100

Why did you remove the blank line? No need for doing that.

>  additionalProperties: true
>  
>  ...

Best regards,
Krzysztof
RE: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
Posted by JeeHeng Sia 2 years ago 

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, November 29, 2023 4:27 PM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org;
> jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org
> Cc: devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan
> <leyfoon.tan@starfivetech.com>
> Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
> 
> On 29/11/2023 07:00, Sia Jee Heng wrote:
> > Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > index cc4d92f0a1bf..7e2da9eef3db 100644
> > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > @@ -29,7 +29,10 @@ properties:
> >                - starfive,visionfive-2-v1.2a
> >                - starfive,visionfive-2-v1.3b
> >            - const: starfive,jh7110
> > -
> > +      - items:
> > +          - enum:
> > +              - starfive,jh8100-evb
> > +          - const: starfive,jh8100
> 
> Why did you remove the blank line? No need for doing that.
Noted. Will fix it.
> 
> >  additionalProperties: true
> >
> >  ...
> 
> Best regards,
> Krzysztof

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.