[v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

[PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

Posted by Jonathan Marek 2 years, 1 month ago

Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.

Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
v2: fixed the Fixes: line

 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d..89a6344bc865 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
 		if (phy->cphy_mode) {
 			vreg_ctrl_0 = 0x45;
-			vreg_ctrl_1 = 0x45;
+			vreg_ctrl_1 = 0x41;
 			glbl_rescode_top_ctrl = 0x00;
 			glbl_rescode_bot_ctrl = 0x00;
 		} else {
-- 
2.26.1

Re: [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

Posted by Abhinav Kumar 2 years, 1 month ago

On Thu, 09 Nov 2023 19:02:14 -0500, Jonathan Marek wrote:
> Use the same value as the downstream driver. This change is needed for CPHY
> mode to work correctly.
> 
> 

Applied, thanks!

[1/1] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy
      https://gitlab.freedesktop.org/drm/msm/-/commit/b3e0f94d1570

Best regards,
-- 
Abhinav Kumar <quic_abhinavk@quicinc.com>

Re: [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

Posted by Abhinav Kumar 2 years, 1 month ago


On 11/9/2023 4:02 PM, Jonathan Marek wrote:
> Use the same value as the downstream driver. This change is needed for CPHY
> mode to work correctly.
> 
> Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> v2: fixed the Fixes: line
> 
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 

Good catch !

LGTM

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 3b1ed02f644d..89a6344bc865 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
>   	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>   		if (phy->cphy_mode) {
>   			vreg_ctrl_0 = 0x45;
> -			vreg_ctrl_1 = 0x45;
> +			vreg_ctrl_1 = 0x41;
>   			glbl_rescode_top_ctrl = 0x00;
>   			glbl_rescode_bot_ctrl = 0x00;
>   		} else {

Re: [Freedreno] [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

Posted by Abhinav Kumar 2 years, 1 month ago


On 11/16/2023 12:36 PM, Abhinav Kumar wrote:
> 
> 
> On 11/9/2023 4:02 PM, Jonathan Marek wrote:
>> Use the same value as the downstream driver. This change is needed for 
>> CPHY
>> mode to work correctly.
>>
>> Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")

One error here. We need 12 chars of SHA but you have 13 otherwise 
checkpatch cries

Fixes: 8b034e677111 ("drm/msm/dsi: add support for DSI-PHY on SM8550")

Will fix this up while applying.

>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>> v2: fixed the Fixes: line
>>
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
> 
> Good catch !
> 
> LGTM
> 
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> 
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 3b1ed02f644d..89a6344bc865 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy 
>> *phy,
>>       if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>>           if (phy->cphy_mode) {
>>               vreg_ctrl_0 = 0x45;
>> -            vreg_ctrl_1 = 0x45;
>> +            vreg_ctrl_1 = 0x41;
>>               glbl_rescode_top_ctrl = 0x00;
>>               glbl_rescode_bot_ctrl = 0x00;
>>           } else {