On 10/25/2023 3:33 AM, Muralidhara M K wrote:
> From: Muralidhara M K <muralidhara.mk@amd.com>
>
> Read correct register bit fields for cs_fabric_id for
> address translation to work.
>
What is the problem exactly?
> Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
> ---
> drivers/ras/amd/atl/reg_fields.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ras/amd/atl/reg_fields.h b/drivers/ras/amd/atl/reg_fields.h
> index c3853a25217b..6b60091f235b 100644
> --- a/drivers/ras/amd/atl/reg_fields.h
> +++ b/drivers/ras/amd/atl/reg_fields.h
> @@ -28,14 +28,14 @@
> * Rev Fieldname Bits
> *
> * D18F0x50 [Fabric Block Instance Information 3]
> - * DF2 BlockFabricId [19:8]
> + * DF2 BlockFabricId [13:8]
DF2 should be [15:8]
> * DF3 BlockFabricId [19:8]
DF3 should be [13:8]
> * DF3p5 BlockFabricId [19:8]
> * DF4 BlockFabricId [19:8]
> - * DF4p5 BlockFabricId [15:8]
> + * DF4p5 BlockFabricId [19:8]
DF4p5 is correctly listed as [15:8].
Special cases can be listed separately.
> */
> -#define DF2_CS_FABRIC_ID GENMASK(19, 8)
> -#define DF4p5_CS_FABRIC_ID GENMASK(15, 8)
> +#define DF2_CS_FABRIC_ID GENMASK(13, 8)
> +#define DF4p5_CS_FABRIC_ID GENMASK(19, 8)
>
Even though the most significant bit changes between DF versions, it
looks like the upper bits are all reserved/Read-as-Zero. So we can
document the correct field, and use an expanded/inclusive field (like
[19:8]) for code simplification. And make a note of this for reference.
Thanks,
Yazen