riscv: dts: sophgo: remove address-cells from intc node

[PATCH v1] riscv: dts: sophgo: remove address-cells from intc node

Posted by Conor Dooley 2 years, 2 months ago

From: Conor Dooley <conor.dooley@microchip.com>

A recent submission [1] from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus, highlighting that
the new cv1800b DT has been incorrectly using #address-cells.
It has no child nodes, so #address-cells is not needed. Remove it.

Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Chao Wei <chao.wei@sophgo.com>
CC: Chen Wang <unicorn_wang@outlook.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: devicetree@vger.kernel.org
CC: linux-riscv@lists.infradead.org
CC: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..aec6401a467b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -34,7 +34,6 @@ cpu0: cpu@0 {
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
-				#address-cells = <0>;
 				#interrupt-cells = <1>;
 			};
 		};
-- 
2.39.2

Re: [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node

Posted by Chen Wang 2 years, 2 months ago

On 2023/10/24 16:20, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> A recent submission [1] from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus, highlighting that
> the new cv1800b DT has been incorrectly using #address-cells.
> It has no child nodes, so #address-cells is not needed. Remove it.
>
> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> CC: Chao Wei <chao.wei@sophgo.com>
> CC: Chen Wang <unicorn_wang@outlook.com>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Paul Walmsley <paul.walmsley@sifive.com>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: Albert Ou <aou@eecs.berkeley.edu>
> CC: devicetree@vger.kernel.org
> CC: linux-riscv@lists.infradead.org
> CC: linux-kernel@vger.kernel.org
> ---
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..aec6401a467b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
>   			cpu0_intc: interrupt-controller {
>   				compatible = "riscv,cpu-intc";
>   				interrupt-controller;
> -				#address-cells = <0>;
>   				#interrupt-cells = <1>;
>   			};
>   		};

Acked-by: Chen Wang <unicorn_wang@outlook.com>

Thanks，btw, will it be merged in 6.7?

Looping Jisheng who is working on Duo/cv1800b.

Re: [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node

Posted by Jisheng Zhang 2 years, 2 months ago

On Wed, Oct 25, 2023 at 08:48:57AM +0800, Chen Wang wrote:
> 
> On 2023/10/24 16:20, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > A recent submission [1] from Rob has added additionalProperties: false
> > to the interrupt-controller child node of RISC-V cpus, highlighting that
> > the new cv1800b DT has been incorrectly using #address-cells.
> > It has no child nodes, so #address-cells is not needed. Remove it.
> > 
> > Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
> > Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Nice catch!

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>


> > ---
> > CC: Chao Wei <chao.wei@sophgo.com>
> > CC: Chen Wang <unicorn_wang@outlook.com>
> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > CC: Paul Walmsley <paul.walmsley@sifive.com>
> > CC: Palmer Dabbelt <palmer@dabbelt.com>
> > CC: Albert Ou <aou@eecs.berkeley.edu>
> > CC: devicetree@vger.kernel.org
> > CC: linux-riscv@lists.infradead.org
> > CC: linux-kernel@vger.kernel.org
> > ---
> >   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
> >   1 file changed, 1 deletion(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index df40e87ee063..aec6401a467b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -34,7 +34,6 @@ cpu0: cpu@0 {
> >   			cpu0_intc: interrupt-controller {
> >   				compatible = "riscv,cpu-intc";
> >   				interrupt-controller;
> > -				#address-cells = <0>;
> >   				#interrupt-cells = <1>;
> >   			};
> >   		};
> 
> Acked-by: Chen Wang <unicorn_wang@outlook.com>
> 
> Thanks，btw, will it be merged in 6.7?

Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.

> 
> Looping Jisheng who is working on Duo/cv1800b.
>

Re: [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node

Posted by Conor Dooley 2 years, 2 months ago

On Wed, Oct 25, 2023 at 11:13:39PM +0800, Jisheng Zhang wrote:

> > Thanks，btw, will it be merged in 6.7?
> 
> Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.

Yup. There's no harmful affects at runtime, it's just a fix for some
dtbs_check warnings that I noticed in linux-next. I'll send it as part
of a fixes PR at some point after -rc1.

Cheers,
Conor.