[v1] Add support for the Mobileye EyeQ5 SoC

[PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code

Posted by Gregory CLEMENT 2 years, 3 months ago

The code clearing BSS already use macro or use correct instruction
depending id the CPU is 32 bits or 64 bits. However, a few
instructions remained 32 bits only.

By using the accurate MACRO, it is now possible to deal with memory
address beyond 32 bits. As a side effect, when using 64bits processor,
it also divides the loop number needed to clear the BSS by 2.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/mips/boot/compressed/head.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 5795d0af1e1b..d237a834b85e 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -25,8 +25,8 @@
 	/* Clear BSS */
 	PTR_LA	a0, _edata
 	PTR_LA	a2, _end
-1:	sw	zero, 0(a0)
-	addiu	a0, a0, 4
+1:	PTR_S	zero, 0(a0)
+	PTR_ADDIU a0, a0, PTRSIZE
 	bne	a2, a0, 1b
 
 	PTR_LA	a0, (.heap)	     /* heap address */
-- 
2.40.1

Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code

Posted by Florian Fainelli 2 years, 2 months ago


On 10/4/2023 9:10 AM, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits.

s/id/if/

> However, a few
> instructions remained 32 bits only.
> 
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>

> ---
>   arch/mips/boot/compressed/head.S | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 5795d0af1e1b..d237a834b85e 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -25,8 +25,8 @@
>   	/* Clear BSS */
>   	PTR_LA	a0, _edata
>   	PTR_LA	a2, _end
> -1:	sw	zero, 0(a0)
> -	addiu	a0, a0, 4
> +1:	PTR_S	zero, 0(a0)
> +	PTR_ADDIU a0, a0, PTRSIZE
>   	bne	a2, a0, 1b
>   
>   	PTR_LA	a0, (.heap)	     /* heap address */

-- 
Florian

Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code

Posted by Philippe Mathieu-Daudé 2 years, 2 months ago

On 4/10/23 18:10, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits. However, a few
> instructions remained 32 bits only.
> 
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>   arch/mips/boot/compressed/head.S | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>