The initialization state of the EIC module is a high level trigger.
If it is currently a high level, the interrupt condition is met at
this time, and the EIC interrupt has a latch capability, which will
cause an interrupt to occur after booting. To avoid this, When setting
the EIC interrupt trigger type, clear the interrupt once.
Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
---
drivers/gpio/gpio-eic-sprd.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
index bfa8a4c7515a..96f1c7fd3988 100644
--- a/drivers/gpio/gpio-eic-sprd.c
+++ b/drivers/gpio/gpio-eic-sprd.c
@@ -375,29 +375,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
@@ -410,29 +415,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
--
2.17.1
On 9/21/2023 5:00 PM, Wenhua Lin wrote: > The initialization state of the EIC module is a high level trigger. > If it is currently a high level, the interrupt condition is met at > this time, and the EIC interrupt has a latch capability, which will > cause an interrupt to occur after booting. To avoid this, When setting > the EIC interrupt trigger type, clear the interrupt once. With Andy's comments, Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> > Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com> > --- > drivers/gpio/gpio-eic-sprd.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c > index bfa8a4c7515a..96f1c7fd3988 100644 > --- a/drivers/gpio/gpio-eic-sprd.c > +++ b/drivers/gpio/gpio-eic-sprd.c > @@ -375,29 +375,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_EDGE_FALLING: > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); > + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_EDGE_BOTH: > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_LEVEL_HIGH: > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_level_irq); > break; > case IRQ_TYPE_LEVEL_LOW: > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); > sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); > + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_level_irq); > break; > default: > @@ -410,29 +415,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_EDGE_FALLING: > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); > + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_EDGE_BOTH: > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_edge_irq); > break; > case IRQ_TYPE_LEVEL_HIGH: > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); > + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_level_irq); > break; > case IRQ_TYPE_LEVEL_LOW: > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); > sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); > + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); > irq_set_handler_locked(data, handle_level_irq); > break; > default:
On Thu, Sep 21, 2023 at 05:00:25PM +0800, Wenhua Lin wrote: > The initialization state of the EIC module is a high level trigger. Here you use EIC, in other places eic. Can you, please, be consistent? > If it is currently a high level, the interrupt condition is met at > this time, and the EIC interrupt has a latch capability, which will > cause an interrupt to occur after booting. To avoid this, When setting > the EIC interrupt trigger type, clear the interrupt once. -- With Best Regards, Andy Shevchenko
On Thu, Sep 21, 2023 at 7:24 PM Andy Shevchenko <andy@kernel.org> wrote: > > On Thu, Sep 21, 2023 at 05:00:25PM +0800, Wenhua Lin wrote: > > The initialization state of the EIC module is a high level trigger. > > Here you use EIC, in other places eic. Can you, please, be consistent? Thank you very much for your review. I will fix this issue in patch v3. > > > If it is currently a high level, the interrupt condition is met at > > this time, and the EIC interrupt has a latch capability, which will > > cause an interrupt to occur after booting. To avoid this, When setting > > the EIC interrupt trigger type, clear the interrupt once. > > -- > With Best Regards, > Andy Shevchenko > >
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