drivers/i2c/busses/i2c-octeon-core.c | 198 +++++++++++++++++++---- drivers/i2c/busses/i2c-octeon-core.h | 14 ++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 4 + 3 files changed, 186 insertions(+), 30 deletions(-)
i2c:octeon:Add block-mode r/w
Add support for block mode read/write operations on
Thunderx chips.
When attempting r/w operations of greater then 8 bytes
block mode is used, instead of performing a series of
8 byte reads.
Signed-off-by: Aryan Srivastava <aryan.srivastava@alliedtelesis.co.nz>
---
drivers/i2c/busses/i2c-octeon-core.c | 198 +++++++++++++++++++----
drivers/i2c/busses/i2c-octeon-core.h | 14 ++
drivers/i2c/busses/i2c-thunderx-pcidrv.c | 4 +
3 files changed, 186 insertions(+), 30 deletions(-)
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 845eda70b8ca..4c704262d228 100644
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -130,6 +130,25 @@ static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
}
+static void octeon_i2c_block_enable(struct octeon_i2c *i2c)
+{
+ if (i2c->block_enabled || !TWSI_BLOCK_CTL(i2c))
+ return;
+
+ i2c->block_enabled = true;
+ octeon_i2c_writeq_flush(TWSI_MODE_STRETCH
+ | TWSI_MODE_BLOCK_MODE, i2c->twsi_base + TWSI_MODE(i2c));
+}
+
+static void octeon_i2c_block_disable(struct octeon_i2c *i2c)
+{
+ if (!i2c->block_enabled || !TWSI_BLOCK_CTL(i2c))
+ return;
+
+ i2c->block_enabled = false;
+ octeon_i2c_writeq_flush(TWSI_MODE_STRETCH, i2c->twsi_base + TWSI_MODE(i2c));
+}
+
/**
* octeon_i2c_hlc_wait - wait for an HLC operation to complete
* @i2c: The struct octeon_i2c
@@ -268,6 +287,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
u8 stat;
octeon_i2c_hlc_disable(i2c);
+ octeon_i2c_block_disable(i2c);
octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
ret = octeon_i2c_wait(i2c);
@@ -485,6 +505,37 @@ static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
return ret;
}
+/* Process hlc transaction */
+static int octeon_i2c_hlc_cmd_send(struct octeon_i2c *i2c, u64 cmd)
+{
+ octeon_i2c_hlc_int_clear(i2c);
+ octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
+
+ return octeon_i2c_hlc_wait(i2c);
+}
+
+/* Construct and send i2c transaction core cmd */
+static int octeon_i2c_hlc_cmd(struct octeon_i2c *i2c, struct i2c_msg msg, u64 cmd)
+{
+ if (msg.flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msg.len == 2) {
+ u64 ext = 0;
+
+ cmd |= SW_TWSI_EIA;
+ ext = (u64)msg.buf[0] << SW_TWSI_IA_SHIFT;
+ cmd |= (u64)msg.buf[1] << SW_TWSI_IA_SHIFT;
+ octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
+ } else {
+ cmd |= (u64)msg.buf[0] << SW_TWSI_IA_SHIFT;
+ }
+
+ return octeon_i2c_hlc_cmd_send(i2c, cmd);
+}
+
/* high-level-controller composite write+read, msg0=addr, msg1=data */
static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
{
@@ -499,26 +550,8 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs
/* A */
cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
- if (msgs[0].flags & I2C_M_TEN)
- cmd |= SW_TWSI_OP_10_IA;
- else
- cmd |= SW_TWSI_OP_7_IA;
-
- if (msgs[0].len == 2) {
- u64 ext = 0;
-
- cmd |= SW_TWSI_EIA;
- ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
- cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
- octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
- } else {
- cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
- }
-
- octeon_i2c_hlc_int_clear(i2c);
- octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
-
- ret = octeon_i2c_hlc_wait(i2c);
+ /* Send core command */
+ ret = octeon_i2c_hlc_cmd(i2c, msgs[0], cmd);
if (ret)
goto err;
@@ -579,10 +612,7 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msg
if (set_ext)
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
- octeon_i2c_hlc_int_clear(i2c);
- octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
-
- ret = octeon_i2c_hlc_wait(i2c);
+ ret = octeon_i2c_hlc_cmd_send(i2c, cmd);
if (ret)
goto err;
@@ -594,6 +624,106 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msg
return ret;
}
+/**
+ * high-level-controller composite block write+read, msg0=addr, msg1=data
+ * Used in the case where the i2c xfer is for greater than 8 bytes of read data.
+ */
+static int octeon_i2c_hlc_block_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int len, ret = 0;
+ u64 cmd = 0;
+
+ octeon_i2c_hlc_enable(i2c);
+ octeon_i2c_block_enable(i2c);
+
+ /* Write (size - 1) into block control register */
+ len = msgs[1].len - 1;
+ octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c));
+
+ /* Prepare core command */
+ cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
+ cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ /* Send core command */
+ ret = octeon_i2c_hlc_cmd(i2c, msgs[0], cmd);
+ if (ret)
+ return ret;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
+ if ((cmd & SW_TWSI_R) == 0)
+ return octeon_i2c_check_status(i2c, false);
+
+ /* read data in FIFO */
+ octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c));
+ for (int i = 0; i < len; i += 8) {
+ u64 rd = __raw_readq(i2c->twsi_base + TWSI_BLOCK_FIFO(i2c));
+ for (int j = 7; j >= 0; j--)
+ msgs[1].buf[i + (7 - j)] = (rd >> (8 * j)) & 0xff;
+ }
+
+ octeon_i2c_block_disable(i2c);
+ return ret;
+}
+
+/**
+ * high-level-controller composite block write+write, m[0]len<=2, m[1]len<=1024
+ * Used in the case where the i2c xfer is for greater than 8 bytes of write data.
+ */
+static int octeon_i2c_hlc_block_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ bool set_ext = false;
+ int i, j, len, ret = 0;
+ u64 cmd, ext = 0;
+
+ octeon_i2c_hlc_enable(i2c);
+ octeon_i2c_block_enable(i2c);
+
+ /* Write (size - 1) into block control register */
+ len = msgs[1].len - 1;
+ octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c));
+
+ /* Prepare core command */
+ cmd = SW_TWSI_V | SW_TWSI_SOVR;
+ cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msgs[0].len == 2) {
+ cmd |= SW_TWSI_EIA;
+ ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ set_ext = true;
+ cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
+ } else {
+ cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ }
+
+ /* Write msg into FIFO buffer */
+ octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c));
+ for (i = 0; i < len; i += 8) {
+ u64 buf = 0;
+ for (j = 7; j >= 0; j--)
+ buf |= (msgs[1].buf[i + (7 - j)] << (8 * j));
+ octeon_i2c_writeq_flush(buf, i2c->twsi_base + TWSI_BLOCK_FIFO(i2c));
+ }
+ if (set_ext)
+ octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
+
+ /* Send command to core (send data in FIFO) */
+ ret = octeon_i2c_hlc_cmd_send(i2c, cmd);
+ if (ret)
+ return ret;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
+ if ((cmd & SW_TWSI_R) == 0)
+ return octeon_i2c_check_status(i2c, false);
+
+ octeon_i2c_block_disable(i2c);
+ return ret;
+}
+
/**
* octeon_i2c_xfer - The driver's master_xfer function
* @adap: Pointer to the i2c_adapter structure
@@ -619,13 +749,21 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
if ((msgs[0].flags & I2C_M_RD) == 0 &&
(msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
msgs[0].len > 0 && msgs[0].len <= 2 &&
- msgs[1].len > 0 && msgs[1].len <= 8 &&
+ msgs[1].len > 0 &&
msgs[0].addr == msgs[1].addr) {
- if (msgs[1].flags & I2C_M_RD)
- ret = octeon_i2c_hlc_comp_read(i2c, msgs);
- else
- ret = octeon_i2c_hlc_comp_write(i2c, msgs);
- goto out;
+ if (msgs[1].len <= 8) {
+ if (msgs[1].flags & I2C_M_RD)
+ ret = octeon_i2c_hlc_comp_read(i2c, msgs);
+ else
+ ret = octeon_i2c_hlc_comp_write(i2c, msgs);
+ goto out;
+ } else if (msgs[1].len <= 1024 && TWSI_BLOCK_CTL(i2c)) {
+ if (msgs[1].flags & I2C_M_RD)
+ ret = octeon_i2c_hlc_block_comp_read(i2c, msgs);
+ else
+ ret = octeon_i2c_hlc_block_comp_write(i2c, msgs);
+ goto out;
+ }
}
}
diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h
index 9bb9f64fdda0..81fcf413c890 100644
--- a/drivers/i2c/busses/i2c-octeon-core.h
+++ b/drivers/i2c/busses/i2c-octeon-core.h
@@ -85,6 +85,11 @@
#define TWSI_INT_SDA BIT_ULL(10)
#define TWSI_INT_SCL BIT_ULL(11)
+#define TWSI_MODE_STRETCH BIT_ULL(1)
+#define TWSI_MODE_BLOCK_MODE BIT_ULL(2)
+
+#define TWSI_BLOCK_STS_RESET_PTR BIT_ULL(0)
+#define TWSI_BLOCK_STS_BUSY BIT_ULL(1)
#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
/* Register offsets */
@@ -92,11 +97,19 @@ struct octeon_i2c_reg_offset {
unsigned int sw_twsi;
unsigned int twsi_int;
unsigned int sw_twsi_ext;
+ unsigned int twsi_mode;
+ unsigned int twsi_block_ctl;
+ unsigned int twsi_block_sts;
+ unsigned int twsi_block_fifo;
};
#define SW_TWSI(x) (x->roff.sw_twsi)
#define TWSI_INT(x) (x->roff.twsi_int)
#define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext)
+#define TWSI_MODE(x) (x->roff.twsi_mode)
+#define TWSI_BLOCK_CTL(x) (x->roff.twsi_block_ctl)
+#define TWSI_BLOCK_STS(x) (x->roff.twsi_block_sts)
+#define TWSI_BLOCK_FIFO(x) (x->roff.twsi_block_fifo)
struct octeon_i2c {
wait_queue_head_t queue;
@@ -110,6 +123,7 @@ struct octeon_i2c {
void __iomem *twsi_base;
struct device *dev;
bool hlc_enabled;
+ bool block_enabled;
bool broken_irq_mode;
bool broken_irq_check;
void (*int_enable)(struct octeon_i2c *);
diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
index a77cd86fe75e..abde98117d7e 100644
--- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c
+++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
@@ -165,6 +165,10 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev,
i2c->roff.sw_twsi = 0x1000;
i2c->roff.twsi_int = 0x1010;
i2c->roff.sw_twsi_ext = 0x1018;
+ i2c->roff.twsi_mode = 0x1038;
+ i2c->roff.twsi_block_ctl = 0x1048;
+ i2c->roff.twsi_block_sts = 0x1050;
+ i2c->roff.twsi_block_fifo = 0x1058;
i2c->dev = dev;
pci_set_drvdata(pdev, i2c);
--
2.42.0Hi Aryan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on linus/master v6.6-rc1 next-20230911]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Aryan-Srivastava/THUNDERX_I2C_BLOCK_MODE/20230912-084721
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/for-next
patch link: https://lore.kernel.org/r/20230912002706.2393450-1-aryan.srivastava%40alliedtelesis.co.nz
patch subject: [PATCH] THUNDERX_I2C_BLOCK_MODE
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20230912/202309121146.BqM4z7k7-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230912/202309121146.BqM4z7k7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309121146.BqM4z7k7-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/i2c/busses/i2c-octeon-core.c:632: warning: Function parameter or member 'i2c' not described in 'octeon_i2c_hlc_block_comp_read'
>> drivers/i2c/busses/i2c-octeon-core.c:632: warning: Function parameter or member 'msgs' not described in 'octeon_i2c_hlc_block_comp_read'
>> drivers/i2c/busses/i2c-octeon-core.c:632: warning: expecting prototype for high(). Prototype was for octeon_i2c_hlc_block_comp_read() instead
>> drivers/i2c/busses/i2c-octeon-core.c:673: warning: Function parameter or member 'i2c' not described in 'octeon_i2c_hlc_block_comp_write'
>> drivers/i2c/busses/i2c-octeon-core.c:673: warning: Function parameter or member 'msgs' not described in 'octeon_i2c_hlc_block_comp_write'
>> drivers/i2c/busses/i2c-octeon-core.c:673: warning: expecting prototype for high(). Prototype was for octeon_i2c_hlc_block_comp_write() instead
vim +632 drivers/i2c/busses/i2c-octeon-core.c
626
627 /**
628 * high-level-controller composite block write+read, msg0=addr, msg1=data
629 * Used in the case where the i2c xfer is for greater than 8 bytes of read data.
630 */
631 static int octeon_i2c_hlc_block_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
> 632 {
633 int len, ret = 0;
634 u64 cmd = 0;
635
636 octeon_i2c_hlc_enable(i2c);
637 octeon_i2c_block_enable(i2c);
638
639 /* Write (size - 1) into block control register */
640 len = msgs[1].len - 1;
641 octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c));
642
643 /* Prepare core command */
644 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
645 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
646
647 /* Send core command */
648 ret = octeon_i2c_hlc_cmd(i2c, msgs[0], cmd);
649 if (ret)
650 return ret;
651
652 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
653 if ((cmd & SW_TWSI_R) == 0)
654 return octeon_i2c_check_status(i2c, false);
655
656 /* read data in FIFO */
657 octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c));
658 for (int i = 0; i < len; i += 8) {
659 u64 rd = __raw_readq(i2c->twsi_base + TWSI_BLOCK_FIFO(i2c));
660 for (int j = 7; j >= 0; j--)
661 msgs[1].buf[i + (7 - j)] = (rd >> (8 * j)) & 0xff;
662 }
663
664 octeon_i2c_block_disable(i2c);
665 return ret;
666 }
667
668 /**
669 * high-level-controller composite block write+write, m[0]len<=2, m[1]len<=1024
670 * Used in the case where the i2c xfer is for greater than 8 bytes of write data.
671 */
672 static int octeon_i2c_hlc_block_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
> 673 {
674 bool set_ext = false;
675 int i, j, len, ret = 0;
676 u64 cmd, ext = 0;
677
678 octeon_i2c_hlc_enable(i2c);
679 octeon_i2c_block_enable(i2c);
680
681 /* Write (size - 1) into block control register */
682 len = msgs[1].len - 1;
683 octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c));
684
685 /* Prepare core command */
686 cmd = SW_TWSI_V | SW_TWSI_SOVR;
687 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
688
689 if (msgs[0].flags & I2C_M_TEN)
690 cmd |= SW_TWSI_OP_10_IA;
691 else
692 cmd |= SW_TWSI_OP_7_IA;
693
694 if (msgs[0].len == 2) {
695 cmd |= SW_TWSI_EIA;
696 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
697 set_ext = true;
698 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
699 } else {
700 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
701 }
702
703 /* Write msg into FIFO buffer */
704 octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c));
705 for (i = 0; i < len; i += 8) {
706 u64 buf = 0;
707 for (j = 7; j >= 0; j--)
708 buf |= (msgs[1].buf[i + (7 - j)] << (8 * j));
709 octeon_i2c_writeq_flush(buf, i2c->twsi_base + TWSI_BLOCK_FIFO(i2c));
710 }
711 if (set_ext)
712 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
713
714 /* Send command to core (send data in FIFO) */
715 ret = octeon_i2c_hlc_cmd_send(i2c, cmd);
716 if (ret)
717 return ret;
718
719 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
720 if ((cmd & SW_TWSI_R) == 0)
721 return octeon_i2c_check_status(i2c, false);
722
723 octeon_i2c_block_disable(i2c);
724 return ret;
725 }
726
--
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