Lengths of SG pointers are in big-endian

Fixes: 37d79d059606 ("octeon_ep: add Tx/Rx processing and interrupt support")
Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
---
 drivers/net/ethernet/marvell/octeon_ep/octep_tx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
index 5a520d37bea0..7e99486c274b 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
@@ -69,12 +69,12 @@ int octep_iq_process_completions(struct octep_iq *iq, u16 budget)
 		compl_sg++;
 
 		dma_unmap_single(iq->dev, tx_buffer->sglist[0].dma_ptr[0],
-				 tx_buffer->sglist[0].len[0], DMA_TO_DEVICE);
+				 tx_buffer->sglist[0].len[3], DMA_TO_DEVICE);
 
 		i = 1; /* entry 0 is main skb, unmapped above */
 		while (frags--) {
 			dma_unmap_page(iq->dev, tx_buffer->sglist[i >> 2].dma_ptr[i & 3],
-				       tx_buffer->sglist[i >> 2].len[i & 3], DMA_TO_DEVICE);
+				       tx_buffer->sglist[i >> 2].len[3 - (i & 3)], DMA_TO_DEVICE);
 			i++;
 		}
 
-- 
2.25.1

On Mon, Sep 11, 2023 at 02:23:06AM -0700, Shinas Rasheed wrote:
> Lengths of SG pointers are in big-endian
> 
> Fixes: 37d79d059606 ("octeon_ep: add Tx/Rx processing and interrupt support")
> Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
> ---
>  drivers/net/ethernet/marvell/octeon_ep/octep_tx.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
> index 5a520d37bea0..7e99486c274b 100644
> --- a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
> +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c
> @@ -69,12 +69,12 @@ int octep_iq_process_completions(struct octep_iq *iq, u16 budget)
>  		compl_sg++;
>  
>  		dma_unmap_single(iq->dev, tx_buffer->sglist[0].dma_ptr[0],
> -				 tx_buffer->sglist[0].len[0], DMA_TO_DEVICE);
> +				 tx_buffer->sglist[0].len[3], DMA_TO_DEVICE);
>  
>  		i = 1; /* entry 0 is main skb, unmapped above */
>  		while (frags--) {
>  			dma_unmap_page(iq->dev, tx_buffer->sglist[i >> 2].dma_ptr[i & 3],
> -				       tx_buffer->sglist[i >> 2].len[i & 3], DMA_TO_DEVICE);
> +				       tx_buffer->sglist[i >> 2].len[3 - (i & 3)], DMA_TO_DEVICE);
>  			i++;
>  		}

Hi Shinas,

is this change also needed in octep_iq_process_completions() ?
The code there looks rather similar.

Hi Simon,

This change is required in octep_iq_process_completions, as given in the patch,
since the scatter gather pointer lengths arrive as big-endian in hardware.

On Tue, 2023-09-12 at 00:04 -0700, Shinas Rasheed wrote:
> This change is required in octep_iq_process_completions, as given in the patch,
> since the scatter gather pointer lengths arrive as big-endian in hardware.

I guess Simon intended asking about octep_iq_free_pending(), and AFAICT
your reply confirm that the change is required there, too.

Additionally the changelog really need to be expanded. I don't
understand how this change relates to endianess: if the ring format is
big endian I expect some be16_to_cpu(len) instead of complement-to-4 of
indexes.

Please clarify and expand the changelog, thanks!

Paolo