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[PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

Gokul Sriram Palanisamy posted 3 patches 2 years, 3 months ago
There is a newer version of this series
[PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Gokul Sriram Palanisamy 2 years, 3 months ago 
Add the APCS, A53 PLL, cpu-opp-table nodes to set
the CPU frequency at optimal range.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..05843517312c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -36,6 +37,8 @@ CPU0: cpu@0 {
 			reg = <0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU1: cpu@1 {
@@ -44,6 +47,8 @@ CPU1: cpu@1 {
 			reg = <0x1>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		L2_0: l2-cache {
@@ -54,6 +59,17 @@ L2_0: l2-cache {
 		};
 	};
 
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+
 	firmware {
 		scm {
 			compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -181,6 +197,24 @@ v2m1: v2m@1000 {
 			};
 		};
 
+		a53pll: clock@b116000 {
+			compatible = "qcom,ipq5018-a53pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
+		apcs_glb: mailbox@b111000 {
+			compatible = "qcom,ipq5018-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a53pll>, <&xo_board_clk>;
+			clock-names = "pll", "xo";
+			#mbox-cells = <1>;
+		};
+
 		timer@b120000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
-- 
2.34.1
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Krzysztof Kozlowski 2 years, 3 months ago 
On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> the CPU frequency at optimal range.
> 
> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..05843517312c 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>  #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/clock/qcom,apss-ipq.h>

c is before r.

>  
>  / {
>  	interrupt-parent = <&intc>;
> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>  			reg = <0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			operating-points-v2 = <&cpu_opp_table>;
>  		};
>  
>  		CPU1: cpu@1 {
> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>  			reg = <0x1>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			operating-points-v2 = <&cpu_opp_table>;
>  		};
>  
>  		L2_0: l2-cache {
> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>  		};
>  	};
>  
> +	cpu_opp_table: opp-table-cpu {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-1008000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <200000>;

And the rest of OPPs?

> +		};
> +	};
> +
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-ipq5018", "qcom,scm";
> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
>  			};
>  		};
>  
> +		a53pll: clock@b116000 {
> +			compatible = "qcom,ipq5018-a53pll";
> +			reg = <0x0b116000 0x40>;
> +			#clock-cells = <0>;
> +			clocks = <&xo_board_clk>;
> +			clock-names = "xo";
> +		};
> +
> +		apcs_glb: mailbox@b111000 {

0xb111000 looks lower than 0x116000.

> +			compatible = "qcom,ipq5018-apcs-apps-global",
> +				     "qcom,ipq6018-apcs-apps-global";
> +			reg = <0x0b111000 0x1000>;

Best regards,
Krzysztof
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Robert Marko 2 years, 3 months ago 
On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
>> the CPU frequency at optimal range.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>>   1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..05843517312c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> c is before r.
>
>>   
>>   / {
>>   	interrupt-parent = <&intc>;
>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>>   			reg = <0x0>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		CPU1: cpu@1 {
>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>>   			reg = <0x1>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		L2_0: l2-cache {
>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>>   		};
>>   	};
>>   
>> +	cpu_opp_table: opp-table-cpu {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-1008000000 {
>> +			opp-hz = /bits/ 64 <1008000000>;
>> +			opp-microvolt = <1100000>;
>> +			clock-latency-ns = <200000>;
> And the rest of OPPs?
Hi Krzysztof,
IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
by default from the bootloader so there is only one OPP.

I am glad to see more SoC-s gaining CPUFreq support.

Regards,
Robert
>
>> +		};
>> +	};
>> +
>>   	firmware {
>>   		scm {
>>   			compatible = "qcom,scm-ipq5018", "qcom,scm";
>> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
>>   			};
>>   		};
>>   
>> +		a53pll: clock@b116000 {
>> +			compatible = "qcom,ipq5018-a53pll";
>> +			reg = <0x0b116000 0x40>;
>> +			#clock-cells = <0>;
>> +			clocks = <&xo_board_clk>;
>> +			clock-names = "xo";
>> +		};
>> +
>> +		apcs_glb: mailbox@b111000 {
> 0xb111000 looks lower than 0x116000.
>
>> +			compatible = "qcom,ipq5018-apcs-apps-global",
>> +				     "qcom,ipq6018-apcs-apps-global";
>> +			reg = <0x0b111000 0x1000>;
> Best regards,
> Krzysztof
>
>
>
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Gokul Sriram P 2 years, 3 months ago 
[...]
>>>   +        a53pll: clock@b116000 {
>>> +            compatible = "qcom,ipq5018-a53pll";
>>> +            reg = <0x0b116000 0x40>;
>>> +            #clock-cells = <0>;
>>> +            clocks = <&xo_board_clk>;
>>> +            clock-names = "xo";
>>> +        };
>>> +
>>> +        apcs_glb: mailbox@b111000 {
>> 0xb111000 looks lower than 0x116000.
Sure, will update.

Regards,
Gokul
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Krzysztof Kozlowski 2 years, 3 months ago 
On 29/08/2023 12:56, Robert Marko wrote:
> 
> On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
>> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
>>> the CPU frequency at optimal range.
>>>
>>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>>>   1 file changed, 34 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> index 9f13d2dcdfd5..05843517312c 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> @@ -8,6 +8,7 @@
>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>> c is before r.
>>
>>>   
>>>   / {
>>>   	interrupt-parent = <&intc>;
>>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>>>   			reg = <0x0>;
>>>   			enable-method = "psci";
>>>   			next-level-cache = <&L2_0>;
>>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +			operating-points-v2 = <&cpu_opp_table>;
>>>   		};
>>>   
>>>   		CPU1: cpu@1 {
>>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>>>   			reg = <0x1>;
>>>   			enable-method = "psci";
>>>   			next-level-cache = <&L2_0>;
>>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +			operating-points-v2 = <&cpu_opp_table>;
>>>   		};
>>>   
>>>   		L2_0: l2-cache {
>>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>>>   		};
>>>   	};
>>>   
>>> +	cpu_opp_table: opp-table-cpu {
>>> +		compatible = "operating-points-v2";
>>> +		opp-shared;
>>> +
>>> +		opp-1008000000 {
>>> +			opp-hz = /bits/ 64 <1008000000>;
>>> +			opp-microvolt = <1100000>;
>>> +			clock-latency-ns = <200000>;
>> And the rest of OPPs?
> Hi Krzysztof,
> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> by default from the bootloader so there is only one OPP.

Isn't this contradictory? If it is running at 800 initially, then it
supports running at 800...


Best regards,
Krzysztof
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Robert Marko 2 years, 3 months ago 
On Tue, 29 Aug 2023 at 13:10, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 29/08/2023 12:56, Robert Marko wrote:
> >
> > On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> >> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> >>> the CPU frequency at optimal range.
> >>>
> >>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> >>> ---
> >>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
> >>>   1 file changed, 34 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> index 9f13d2dcdfd5..05843517312c 100644
> >>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> @@ -8,6 +8,7 @@
> >>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> >> c is before r.
> >>
> >>>
> >>>   / {
> >>>     interrupt-parent = <&intc>;
> >>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> >>>                     reg = <0x0>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             CPU1: cpu@1 {
> >>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> >>>                     reg = <0x1>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             L2_0: l2-cache {
> >>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
> >>>             };
> >>>     };
> >>>
> >>> +   cpu_opp_table: opp-table-cpu {
> >>> +           compatible = "operating-points-v2";
> >>> +           opp-shared;
> >>> +
> >>> +           opp-1008000000 {
> >>> +                   opp-hz = /bits/ 64 <1008000000>;
> >>> +                   opp-microvolt = <1100000>;
> >>> +                   clock-latency-ns = <200000>;
> >> And the rest of OPPs?
> > Hi Krzysztof,
> > IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> > by default from the bootloader so there is only one OPP.
>
> Isn't this contradictory? If it is running at 800 initially, then it
> supports running at 800...

I can only guess that it's not validated at 800MHz.

Regards,
Robert
>
>
> Best regards,
> Krzysztof
>
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Gokul Sriram P 2 years, 3 months ago 
>>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>>>    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>> c is before r.
  Sure, will update.

[...]
>>>>
>>>>> +   cpu_opp_table: opp-table-cpu {
>>>>> +           compatible = "operating-points-v2";
>>>>> +           opp-shared;
>>>>> +
>>>>> +           opp-1008000000 {
>>>>> +                   opp-hz = /bits/ 64 <1008000000>;
>>>>> +                   opp-microvolt = <1100000>;
>>>>> +                   clock-latency-ns = <200000>;
>>>> And the rest of OPPs?
>>> Hi Krzysztof,
>>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
>>> by default from the bootloader so there is only one OPP.
>> Isn't this contradictory? If it is running at 800 initially, then it
>> supports running at 800...
> I can only guess that it's not validated at 800MHz.
As per the h/w design team, there is negligible power or thermal benefit 
by lowering to 800MHz clock.
Hence, 800MHz opp wasn't included here.
>
> Regards,
> Robert
>>
>> Best regards,
>> Krzysztof
>>
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Dmitry Baryshkov 2 years, 3 months ago 
On Wed, 30 Aug 2023 at 21:32, Gokul Sriram P <quic_gokulsri@quicinc.com> wrote:
>
>
> >>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>>    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>>>>    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> >>>> c is before r.
>   Sure, will update.
>
> [...]
> >>>>
> >>>>> +   cpu_opp_table: opp-table-cpu {
> >>>>> +           compatible = "operating-points-v2";
> >>>>> +           opp-shared;
> >>>>> +
> >>>>> +           opp-1008000000 {
> >>>>> +                   opp-hz = /bits/ 64 <1008000000>;
> >>>>> +                   opp-microvolt = <1100000>;
> >>>>> +                   clock-latency-ns = <200000>;
> >>>> And the rest of OPPs?
> >>> Hi Krzysztof,
> >>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> >>> by default from the bootloader so there is only one OPP.
> >> Isn't this contradictory? If it is running at 800 initially, then it
> >> supports running at 800...
> > I can only guess that it's not validated at 800MHz.
> As per the h/w design team, there is negligible power or thermal benefit
> by lowering to 800MHz clock.
> Hence, 800MHz opp wasn't included here.

Just my 2c. If 800 MHz is supported, it should be included. Even if
just to prevent the kernel from throwing a warning about the CPU
running at the unsupported frequency. Then one can use scheduler
tunings to prevent the CPU from going to 800 MHz state.


-- 
With best wishes
Dmitry
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Gokul Sriram P 2 years, 3 months ago 
On 8/31/2023 1:12 AM, Dmitry Baryshkov wrote:
> On Wed, 30 Aug 2023 at 21:32, Gokul Sriram P <quic_gokulsri@quicinc.com> wrote:
>>
>>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>>     #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>>>>>     #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>>>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>>>> c is before r.
>>    Sure, will update.
>>
>> [...]
>>>>>>> +   cpu_opp_table: opp-table-cpu {
>>>>>>> +           compatible = "operating-points-v2";
>>>>>>> +           opp-shared;
>>>>>>> +
>>>>>>> +           opp-1008000000 {
>>>>>>> +                   opp-hz = /bits/ 64 <1008000000>;
>>>>>>> +                   opp-microvolt = <1100000>;
>>>>>>> +                   clock-latency-ns = <200000>;
>>>>>> And the rest of OPPs?
>>>>> Hi Krzysztof,
>>>>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
>>>>> by default from the bootloader so there is only one OPP.
>>>> Isn't this contradictory? If it is running at 800 initially, then it
>>>> supports running at 800...
>>> I can only guess that it's not validated at 800MHz.
>> As per the h/w design team, there is negligible power or thermal benefit
>> by lowering to 800MHz clock.
>> Hence, 800MHz opp wasn't included here.
> Just my 2c. If 800 MHz is supported, it should be included. Even if
> just to prevent the kernel from throwing a warning about the CPU
> running at the unsupported frequency. Then one can use scheduler
> tunings to prevent the CPU from going to 800 MHz state.

sure, understood. Will add opp at 800MHz. Thanks.

Regards,
Gokul
Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support
Posted by Dmitry Baryshkov 2 years, 3 months ago 
On Tue, 29 Aug 2023 at 13:59, Robert Marko <robimarko@gmail.com> wrote:
>
>
> On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> > On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> >> the CPU frequency at optimal range.
> >>
> >> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> >> ---
> >>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
> >>   1 file changed, 34 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> index 9f13d2dcdfd5..05843517312c 100644
> >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> > c is before r.
> >
> >>
> >>   / {
> >>      interrupt-parent = <&intc>;
> >> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> >>                      reg = <0x0>;
> >>                      enable-method = "psci";
> >>                      next-level-cache = <&L2_0>;
> >> +                    clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >> +                    operating-points-v2 = <&cpu_opp_table>;
> >>              };
> >>
> >>              CPU1: cpu@1 {
> >> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> >>                      reg = <0x1>;
> >>                      enable-method = "psci";
> >>                      next-level-cache = <&L2_0>;
> >> +                    clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >> +                    operating-points-v2 = <&cpu_opp_table>;
> >>              };
> >>
> >>              L2_0: l2-cache {
> >> @@ -54,6 +59,17 @@ L2_0: l2-cache {
> >>              };
> >>      };
> >>
> >> +    cpu_opp_table: opp-table-cpu {
> >> +            compatible = "operating-points-v2";
> >> +            opp-shared;
> >> +
> >> +            opp-1008000000 {
> >> +                    opp-hz = /bits/ 64 <1008000000>;
> >> +                    opp-microvolt = <1100000>;
> >> +                    clock-latency-ns = <200000>;
> > And the rest of OPPs?
> Hi Krzysztof,
> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> by default from the bootloader so there is only one OPP.

If the bootloader sets it to 800 MHz, then this frequency is also
somehow 'supported', isn't it?

> I am glad to see more SoC-s gaining CPUFreq support.

Definitely.

>
> Regards,
> Robert
> >
> >> +            };
> >> +    };
> >> +
> >>      firmware {
> >>              scm {
> >>                      compatible = "qcom,scm-ipq5018", "qcom,scm";
> >> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
> >>                      };
> >>              };
> >>
> >> +            a53pll: clock@b116000 {
> >> +                    compatible = "qcom,ipq5018-a53pll";
> >> +                    reg = <0x0b116000 0x40>;
> >> +                    #clock-cells = <0>;
> >> +                    clocks = <&xo_board_clk>;
> >> +                    clock-names = "xo";
> >> +            };
> >> +
> >> +            apcs_glb: mailbox@b111000 {
> > 0xb111000 looks lower than 0x116000.
> >
> >> +                    compatible = "qcom,ipq5018-apcs-apps-global",
> >> +                                 "qcom,ipq6018-apcs-apps-global";
> >> +                    reg = <0x0b111000 0x1000>;
> > Best regards,
> > Krzysztof
> >
> >
> >



-- 
With best wishes
Dmitry

Patchew 2.1-devel-b67e4c2

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