SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.
Add bindings for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/clock/qcom,sm6115-lpasscc.yaml | 53 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++
2 files changed, 68 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 000000000000..58ee84aed073
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm LPASS core and audio clock controllers provide audio-related resets
+ on SM6115 and its derivatives.
+
+ See also::
+ include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6115-lpassaudiocc
+ - qcom,sm6115-lpasscc
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_audiocc: clock-controller@a6a9000 {
+ compatible = "qcom,sm6115-lpassaudiocc";
+ reg = <0x0a6a9000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ - |
+ lpasscc: clock-controller@a7ec000 {
+ compatible = "qcom,sm6115-lpasscc";
+ reg = <0x0a7ec000 0x1000>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
new file mode 100644
index 000000000000..799274517c9a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+
+/* LPASS CC */
+#define LPASS_SWR_TX_CONFIG_CGCR 0
+
+/* LPASS_AUDIO CC */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+
+#endif
--
2.42.0On 25/08/2023 20:13, Konrad Dybcio wrote:
> SM6115 (and its derivatives or similar SoCs) have a LPASS clock
> controller block which provides audio-related resets.
>
> Add bindings for it.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/clock/qcom,sm6115-lpasscc.yaml | 53 ++++++++++++++++++++++
> include/dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
> new file mode 100644
> index 000000000000..58ee84aed073
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
Everything here looks the same as sc8280xp, so this could be just added
there as enum. The overall LPASS block version is different, but the
resets/clock controller look similar, doesn't it?
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@linaro.org>
> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> +
> +description: |
> + Qualcomm LPASS core and audio clock controllers provide audio-related resets
> + on SM6115 and its derivatives.
> +
> + See also::
> + include/dt-bindings/clock/qcom,sm6115-lpasscc.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sm6115-lpassaudiocc
> + - qcom,sm6115-lpasscc
> +
> + reg:
> + maxItems: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + lpass_audiocc: clock-controller@a6a9000 {
> + compatible = "qcom,sm6115-lpassaudiocc";
> + reg = <0x0a6a9000 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + - |
> + lpasscc: clock-controller@a7ec000 {
> + compatible = "qcom,sm6115-lpasscc";
> + reg = <0x0a7ec000 0x1000>;
> + #reset-cells = <1>;
Also second example is not really needed. The difference is only in the
compatible.
Best regards,
Krzysztof
On 26.08.2023 11:28, Krzysztof Kozlowski wrote: > On 25/08/2023 20:13, Konrad Dybcio wrote: >> SM6115 (and its derivatives or similar SoCs) have a LPASS clock >> controller block which provides audio-related resets. >> >> Add bindings for it. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> .../bindings/clock/qcom,sm6115-lpasscc.yaml | 53 ++++++++++++++++++++++ >> include/dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++ >> 2 files changed, 68 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml >> new file mode 100644 >> index 000000000000..58ee84aed073 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml >> @@ -0,0 +1,53 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm LPASS Core & Audio Clock Controller on SM6115 > > Everything here looks the same as sc8280xp, so this could be just added > there as enum. The overall LPASS block version is different, but the > resets/clock controller look similar, doesn't it? I think the 6115 cc block is a bit different, 8280 has more swr hosts. Maybe Srini would know more. [...] > Also second example is not really needed. The difference is only in the > compatible. Ack Konrad
On 26/08/2023 11:39, Konrad Dybcio wrote: > On 26.08.2023 11:28, Krzysztof Kozlowski wrote: >> On 25/08/2023 20:13, Konrad Dybcio wrote: >>> SM6115 (and its derivatives or similar SoCs) have a LPASS clock >>> controller block which provides audio-related resets. >>> >>> Add bindings for it. >>> >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>> --- >>> .../bindings/clock/qcom,sm6115-lpasscc.yaml | 53 ++++++++++++++++++++++ >>> include/dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++ >>> 2 files changed, 68 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml >>> new file mode 100644 >>> index 000000000000..58ee84aed073 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml >>> @@ -0,0 +1,53 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm LPASS Core & Audio Clock Controller on SM6115 >> >> Everything here looks the same as sc8280xp, so this could be just added >> there as enum. The overall LPASS block version is different, but the >> resets/clock controller look similar, doesn't it? > I think the 6115 cc block is a bit different, 8280 has more swr > hosts. Maybe Srini would know more. Indeed, looking at downstream DTS this is closer to SM8250 and SM8350 than SC8280xp, with some interesting differences. But if you bring it up, you also might fix SM8350, to which I looked a bit but then gave up. Anyway, with the example staying or removed: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
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