Add SC7280 specific register layout and table configs.
Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
1 file changed, 142 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3927eba8e468..514fa14df634 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -177,6 +177,111 @@ static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
};
+static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+};
+
+static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
+};
+
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
@@ -888,6 +993,40 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.regs = ufsphy_v5_regs_layout,
};
+static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets,
+
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sc7280_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
+ .rx = sc7280_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
+ .pcs = sc7280_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8150_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .tx = sm8250_ufsphy_hs_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
+ .rx = sc7280_ufsphy_hs_g4_rx,
+ .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
+ .pcs = sm8150_ufsphy_hs_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ },
+ .clk_list = sm8450_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = ufsphy_v4_regs_layout,
+};
+
static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
@@ -1648,6 +1787,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
}, {
.compatible = "qcom,sa8775p-qmp-ufs-phy",
.data = &sa8775p_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sc7280-qmp-ufs-phy",
+ .data = &sc7280_ufsphy_cfg,
}, {
.compatible = "qcom,sc8180x-qmp-ufs-phy",
.data = &sm8150_ufsphy_cfg,
--
2.17.1On 23/08/2023 12:17, Nitin Rawat wrote:
> Add SC7280 specific register layout and table configs.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
> 1 file changed, 142 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba8e468..514fa14df634 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
[skipped tables programming]
4),
> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .regs = ufsphy_v5_regs_layout,
> };
>
> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets,
> +
> + .tbls = {
> + .serdes = sm8150_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
> + .tx = sc7280_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
> + .rx = sc7280_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
> + .pcs = sc7280_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
> + },
> + .tbls_hs_b = {
> + .serdes = sm8150_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .tx = sm8250_ufsphy_hs_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> + .rx = sc7280_ufsphy_hs_g4_rx,
> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
> + .pcs = sm8150_ufsphy_hs_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + },
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
This doesn't correspond to the bindings. This array has 3 enries, while
in the bindings you have opted for two clocks for this PHY.
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = ufsphy_v4_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .lanes = 2,
>
> @@ -1648,6 +1787,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,sa8775p-qmp-ufs-phy",
> .data = &sa8775p_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc7280-qmp-ufs-phy",
> + .data = &sc7280_ufsphy_cfg,
> }, {
> .compatible = "qcom,sc8180x-qmp-ufs-phy",
> .data = &sm8150_ufsphy_cfg,
> --
> 2.17.1
>
--
With best wishes
Dmitry
On 9/6/2023 1:34 AM, Dmitry Baryshkov wrote:
> On 23/08/2023 12:17, Nitin Rawat wrote:
>> Add SC7280 specific register layout and table configs.
>>
>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
>> 1 file changed, 142 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 3927eba8e468..514fa14df634 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>
> [skipped tables programming]
>
> 4),
Sorry I quite didn't get this comment. what exactly is skipped ?Please
can you help explain?
>> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg
>> sa8775p_ufsphy_cfg = {
>> .regs = ufsphy_v5_regs_layout,
>> };
>>
>> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
>> + .lanes = 2,
>> +
>> + .offsets = &qmp_ufs_offsets,
>> +
>> + .tbls = {
>> + .serdes = sm8150_ufsphy_serdes,
>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
>> + .tx = sc7280_ufsphy_tx,
>> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
>> + .rx = sc7280_ufsphy_rx,
>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
>> + .pcs = sc7280_ufsphy_pcs,
>> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
>> + },
>> + .tbls_hs_b = {
>> + .serdes = sm8150_ufsphy_hs_b_serdes,
>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
>> + },
>> + .tbls_hs_g4 = {
>> + .tx = sm8250_ufsphy_hs_g4_tx,
>> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
>> + .rx = sc7280_ufsphy_hs_g4_rx,
>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
>> + .pcs = sm8150_ufsphy_hs_g4_pcs,
>> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
>> + },
>> + .clk_list = sm8450_ufs_phy_clk_l,
>> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
>
> This doesn't correspond to the bindings. This array has 3 enries, while
> in the bindings you have opted for two clocks for this PHY.
Sure. I'll update the bindings.
>
>> + .vreg_list = qmp_phy_vreg_l,
>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>> + .regs = ufsphy_v4_regs_layout,
>> +};
>> +
>> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
>> .lanes = 2,
>>
>> @@ -1648,6 +1787,9 @@ static const struct of_device_id
>> qmp_ufs_of_match_table[] = {
>> }, {
>> .compatible = "qcom,sa8775p-qmp-ufs-phy",
>> .data = &sa8775p_ufsphy_cfg,
>> + }, {
>> + .compatible = "qcom,sc7280-qmp-ufs-phy",
>> + .data = &sc7280_ufsphy_cfg,
>> }, {
>> .compatible = "qcom,sc8180x-qmp-ufs-phy",
>> .data = &sm8150_ufsphy_cfg,
>> --
>> 2.17.1
>>
>
Thanks,
Nitin
On Fri, 15 Sept 2023 at 19:14, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>
>
>
> On 9/6/2023 1:34 AM, Dmitry Baryshkov wrote:
> > On 23/08/2023 12:17, Nitin Rawat wrote:
> >> Add SC7280 specific register layout and table configs.
> >>
> >> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> >> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> >> ---
> >> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
> >> 1 file changed, 142 insertions(+)
> >>
> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> index 3927eba8e468..514fa14df634 100644
> >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >
> > [skipped tables programming]
> >
> > 4),
> Sorry I quite didn't get this comment. what exactly is skipped ?Please
> can you help explain?
I skipped them, as I didn't have comments for them.
>
>
> >> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg
> >> sa8775p_ufsphy_cfg = {
> >> .regs = ufsphy_v5_regs_layout,
> >> };
> >>
> >> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
> >> + .lanes = 2,
> >> +
> >> + .offsets = &qmp_ufs_offsets,
> >> +
> >> + .tbls = {
> >> + .serdes = sm8150_ufsphy_serdes,
> >> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
> >> + .tx = sc7280_ufsphy_tx,
> >> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
> >> + .rx = sc7280_ufsphy_rx,
> >> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
> >> + .pcs = sc7280_ufsphy_pcs,
> >> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
> >> + },
> >> + .tbls_hs_b = {
> >> + .serdes = sm8150_ufsphy_hs_b_serdes,
> >> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> >> + },
> >> + .tbls_hs_g4 = {
> >> + .tx = sm8250_ufsphy_hs_g4_tx,
> >> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> >> + .rx = sc7280_ufsphy_hs_g4_rx,
> >> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
> >> + .pcs = sm8150_ufsphy_hs_g4_pcs,
> >> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> >> + },
> >> + .clk_list = sm8450_ufs_phy_clk_l,
> >> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> >
> > This doesn't correspond to the bindings. This array has 3 enries, while
> > in the bindings you have opted for two clocks for this PHY.
> Sure. I'll update the bindings.
Are you sure about the third clock? Neither sm8150 nor sm8250 used the
qref clock. Or is that an omission on our side?
>
> >
> >> + .vreg_list = qmp_phy_vreg_l,
> >> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> >> + .regs = ufsphy_v4_regs_layout,
> >> +};
> >> +
> >> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> >> .lanes = 2,
> >>
> >> @@ -1648,6 +1787,9 @@ static const struct of_device_id
> >> qmp_ufs_of_match_table[] = {
> >> }, {
> >> .compatible = "qcom,sa8775p-qmp-ufs-phy",
> >> .data = &sa8775p_ufsphy_cfg,
> >> + }, {
> >> + .compatible = "qcom,sc7280-qmp-ufs-phy",
> >> + .data = &sc7280_ufsphy_cfg,
> >> }, {
> >> .compatible = "qcom,sc8180x-qmp-ufs-phy",
> >> .data = &sm8150_ufsphy_cfg,
> >> --
> >> 2.17.1
> >>
> >
> Thanks,
> Nitin
--
With best wishes
Dmitry
On 9/16/2023 12:03 AM, Dmitry Baryshkov wrote:
> On Fri, 15 Sept 2023 at 19:14, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>>
>>
>>
>> On 9/6/2023 1:34 AM, Dmitry Baryshkov wrote:
>>> On 23/08/2023 12:17, Nitin Rawat wrote:
>>>> Add SC7280 specific register layout and table configs.
>>>>
>>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>> ---
>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
>>>> 1 file changed, 142 insertions(+)
>>>>
>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> index 3927eba8e468..514fa14df634 100644
>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>
>>> [skipped tables programming]
>>>
>>> 4),
>> Sorry I quite didn't get this comment. what exactly is skipped ?Please
>> can you help explain?
>
> I skipped them, as I didn't have comments for them.
>
>>
>>
>>>> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg
>>>> sa8775p_ufsphy_cfg = {
>>>> .regs = ufsphy_v5_regs_layout,
>>>> };
>>>>
>>>> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
>>>> + .lanes = 2,
>>>> +
>>>> + .offsets = &qmp_ufs_offsets,
>>>> +
>>>> + .tbls = {
>>>> + .serdes = sm8150_ufsphy_serdes,
>>>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
>>>> + .tx = sc7280_ufsphy_tx,
>>>> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
>>>> + .rx = sc7280_ufsphy_rx,
>>>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
>>>> + .pcs = sc7280_ufsphy_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
>>>> + },
>>>> + .tbls_hs_b = {
>>>> + .serdes = sm8150_ufsphy_hs_b_serdes,
>>>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
>>>> + },
>>>> + .tbls_hs_g4 = {
>>>> + .tx = sm8250_ufsphy_hs_g4_tx,
>>>> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
>>>> + .rx = sc7280_ufsphy_hs_g4_rx,
>>>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
>>>> + .pcs = sm8150_ufsphy_hs_g4_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
>>>> + },
>>>> + .clk_list = sm8450_ufs_phy_clk_l,
>>>> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
>>>
>>> This doesn't correspond to the bindings. This array has 3 enries, while
>>> in the bindings you have opted for two clocks for this PHY.
>> Sure. I'll update the bindings.
>
> Are you sure about the third clock? Neither sm8150 nor sm8250 used the
> qref clock. Or is that an omission on our side?
>
Hi Dmitry,
For SC7280 we need all the three clocks for this target. Same is being
used in downstream code as well. Hence I would need to update the
binding as well.
Thanks,
Nitin
>>
>>>
>>>> + .vreg_list = qmp_phy_vreg_l,
>>>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>>>> + .regs = ufsphy_v4_regs_layout,
>>>> +};
>>>> +
>>>> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
>>>> .lanes = 2,
>>>>
>>>> @@ -1648,6 +1787,9 @@ static const struct of_device_id
>>>> qmp_ufs_of_match_table[] = {
>>>> }, {
>>>> .compatible = "qcom,sa8775p-qmp-ufs-phy",
>>>> .data = &sa8775p_ufsphy_cfg,
>>>> + }, {
>>>> + .compatible = "qcom,sc7280-qmp-ufs-phy",
>>>> + .data = &sc7280_ufsphy_cfg,
>>>> }, {
>>>> .compatible = "qcom,sc8180x-qmp-ufs-phy",
>>>> .data = &sm8150_ufsphy_cfg,
>>>> --
>>>> 2.17.1
>>>>
>>>
>> Thanks,
>> Nitin
>
>
>
On Sun, 17 Sept 2023 at 17:23, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>
>
>
> On 9/16/2023 12:03 AM, Dmitry Baryshkov wrote:
> > On Fri, 15 Sept 2023 at 19:14, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 9/6/2023 1:34 AM, Dmitry Baryshkov wrote:
> >>> On 23/08/2023 12:17, Nitin Rawat wrote:
> >>>> Add SC7280 specific register layout and table configs.
> >>>>
> >>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>>> ---
> >>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
> >>>> 1 file changed, 142 insertions(+)
> >>>>
> >>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> index 3927eba8e468..514fa14df634 100644
> >>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>
> >>> [skipped tables programming]
> >>>
> >>> 4),
> >> Sorry I quite didn't get this comment. what exactly is skipped ?Please
> >> can you help explain?
> >
> > I skipped them, as I didn't have comments for them.
> >
> >>
> >>
> >>>> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg
> >>>> sa8775p_ufsphy_cfg = {
> >>>> .regs = ufsphy_v5_regs_layout,
> >>>> };
> >>>>
> >>>> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
> >>>> + .lanes = 2,
> >>>> +
> >>>> + .offsets = &qmp_ufs_offsets,
> >>>> +
> >>>> + .tbls = {
> >>>> + .serdes = sm8150_ufsphy_serdes,
> >>>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
> >>>> + .tx = sc7280_ufsphy_tx,
> >>>> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
> >>>> + .rx = sc7280_ufsphy_rx,
> >>>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
> >>>> + .pcs = sc7280_ufsphy_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
> >>>> + },
> >>>> + .tbls_hs_b = {
> >>>> + .serdes = sm8150_ufsphy_hs_b_serdes,
> >>>> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> >>>> + },
> >>>> + .tbls_hs_g4 = {
> >>>> + .tx = sm8250_ufsphy_hs_g4_tx,
> >>>> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> >>>> + .rx = sc7280_ufsphy_hs_g4_rx,
> >>>> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
> >>>> + .pcs = sm8150_ufsphy_hs_g4_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> >>>> + },
> >>>> + .clk_list = sm8450_ufs_phy_clk_l,
> >>>> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> >>>
> >>> This doesn't correspond to the bindings. This array has 3 enries, while
> >>> in the bindings you have opted for two clocks for this PHY.
> >> Sure. I'll update the bindings.
> >
> > Are you sure about the third clock? Neither sm8150 nor sm8250 used the
> > qref clock. Or is that an omission on our side?
> >
>
> Hi Dmitry,
>
> For SC7280 we need all the three clocks for this target. Same is being
> used in downstream code as well. Hence I would need to update the
> binding as well.
Ack, thanks for the confirmation.
>
> Thanks,
> Nitin
>
>
> >>
> >>>
> >>>> + .vreg_list = qmp_phy_vreg_l,
> >>>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> >>>> + .regs = ufsphy_v4_regs_layout,
> >>>> +};
> >>>> +
> >>>> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> >>>> .lanes = 2,
> >>>>
> >>>> @@ -1648,6 +1787,9 @@ static const struct of_device_id
> >>>> qmp_ufs_of_match_table[] = {
> >>>> }, {
> >>>> .compatible = "qcom,sa8775p-qmp-ufs-phy",
> >>>> .data = &sa8775p_ufsphy_cfg,
> >>>> + }, {
> >>>> + .compatible = "qcom,sc7280-qmp-ufs-phy",
> >>>> + .data = &sc7280_ufsphy_cfg,
> >>>> }, {
> >>>> .compatible = "qcom,sc8180x-qmp-ufs-phy",
> >>>> .data = &sm8150_ufsphy_cfg,
> >>>> --
> >>>> 2.17.1
> >>>>
> >>>
> >> Thanks,
> >> Nitin
> >
> >
> >
--
With best wishes
Dmitry
On 8/23/2023 2:47 PM, Nitin Rawat wrote:
> Add SC7280 specific register layout and table configs.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 142 ++++++++++++++++++++++++
> 1 file changed, 142 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba8e468..514fa14df634 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -177,6 +177,111 @@ static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
> };
>
> +static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> +};
> +
> +static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
> +};
> +
> static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> @@ -888,6 +993,40 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .regs = ufsphy_v5_regs_layout,
> };
>
> +static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets,
> +
> + .tbls = {
> + .serdes = sm8150_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
> + .tx = sc7280_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
> + .rx = sc7280_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
> + .pcs = sc7280_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
> + },
> + .tbls_hs_b = {
> + .serdes = sm8150_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .tx = sm8250_ufsphy_hs_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> + .rx = sc7280_ufsphy_hs_g4_rx,
> + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
> + .pcs = sm8150_ufsphy_hs_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + },
> + .clk_list = sm8450_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = ufsphy_v4_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .lanes = 2,
>
> @@ -1648,6 +1787,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,sa8775p-qmp-ufs-phy",
> .data = &sa8775p_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sc7280-qmp-ufs-phy",
> + .data = &sc7280_ufsphy_cfg,
> }, {
> .compatible = "qcom,sc8180x-qmp-ufs-phy",
> .data = &sm8150_ufsphy_cfg,
> --
> 2.17.1
>
Gentle reminder, kindly let me know any further comments.
Thanks,
Nitin
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