drivers/pci/controller/pcie-xilinx-nwl.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-)
The primary,secondary and sub-ordinate bus number registers are updated by
Linux PCI core, so remove code which updates repective fields of type 1
header 18th offset of Root Port configuration space.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
---
changes in v2:
- Code increasing ECAM Size value is added into a seperate patch.
- Modified commit messages.
changes in v1:
- Modified commit messages.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 176686b..a73554e 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -165,8 +165,6 @@ struct nwl_pcie {
u32 ecam_size;
int irq_intx;
int irq_misc;
- u32 ecam_value;
- u8 last_busno;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
struct clk *clk;
@@ -625,7 +623,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
{
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
- u32 breg_val, ecam_val, first_busno = 0;
+ u32 breg_val, ecam_val;
int err;
breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
@@ -675,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
- (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
+ (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT),
E_ECAM_CONTROL);
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
@@ -683,15 +681,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_HI);
- /* Get bus range */
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
- pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
- /* Write primary, secondary and subordinate bus numbers */
- ecam_val = first_busno;
- ecam_val |= (first_busno + 1) << 8;
- ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
- writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
-
if (nwl_pcie_link_up(pcie))
dev_info(dev, "Link is UP\n");
else
@@ -792,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
pcie = pci_host_bridge_priv(bridge);
pcie->dev = dev;
- pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
err = nwl_pcie_parse_dt(pcie, pdev);
if (err) {
--
1.8.3.1Current driver is supports up to 16 buses. The following code fixes to support up to 256 buses. update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM region to detect 256 buses. Update ecam size to 256MB in device tree binding example. Thippeswamy Havalige (2): dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses. Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 1.8.3.1
On Tue, Aug 08, 2023 at 04:07:30PM +0530, Thippeswamy Havalige wrote:
> The primary,secondary and sub-ordinate bus number registers are updated by
> Linux PCI core, so remove code which updates repective fields of type 1
> header 18th offset of Root Port configuration space.
Whoever applies this, please:
- Drop period from subject line
- Add space after comma
- s/repective/respective/
- Fix up "18th"; I suppose this refers to the 18h offset, but the
reference is too low-level and probably unnecessary since we
already listed the affected registers
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
> ---
> changes in v2:
> - Code increasing ECAM Size value is added into a seperate patch.
> - Modified commit messages.
> changes in v1:
> - Modified commit messages.
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 16 ++--------------
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 176686b..a73554e 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -165,8 +165,6 @@ struct nwl_pcie {
> u32 ecam_size;
> int irq_intx;
> int irq_misc;
> - u32 ecam_value;
The removal of "ecam_value" has nothing to do with the PCI core; it
seems more related to the NWL_ECAM_VALUE_DEFAULT change, and I would
either squash it into that patch or make it a separate "no functional
change" cleanup patch.
> - u8 last_busno;
> struct nwl_msi msi;
> struct irq_domain *legacy_irq_domain;
> struct clk *clk;
> @@ -625,7 +623,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
> {
> struct device *dev = pcie->dev;
> struct platform_device *pdev = to_platform_device(dev);
> - u32 breg_val, ecam_val, first_busno = 0;
> + u32 breg_val, ecam_val;
> int err;
>
> breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
> @@ -675,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
> E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
>
> nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
> - (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
> + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT),
> E_ECAM_CONTROL);
>
> nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
> @@ -683,15 +681,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
> nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
> E_ECAM_BASE_HI);
>
> - /* Get bus range */
> - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
> - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
> - /* Write primary, secondary and subordinate bus numbers */
> - ecam_val = first_busno;
> - ecam_val |= (first_busno + 1) << 8;
> - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
> - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
> -
> if (nwl_pcie_link_up(pcie))
> dev_info(dev, "Link is UP\n");
> else
> @@ -792,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
> pcie = pci_host_bridge_priv(bridge);
>
> pcie->dev = dev;
> - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
>
> err = nwl_pcie_parse_dt(pcie, pdev);
> if (err) {
> --
> 1.8.3.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Update ECAM size in example to discover up to 256 buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
---
changes in v2:
None.
changes in v1:
None.
---
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 8976025..426f90a 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -118,7 +118,7 @@ examples:
compatible = "xlnx,nwl-pcie-2.11";
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
--
1.8.3.1On Tue, 8 Aug 2023 16:07:32 +0530 Thippeswamy Havalige <thippeswamy.havalige@amd.com> wrote: Hi, drop the final dot in all commit titles. Hugo Villeneuve. > Update ECAM size in example to discover up to 256 buses. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> > --- > changes in v2: > None. > changes in v1: > None. > --- > Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > index 8976025..426f90a 100644 > --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > @@ -118,7 +118,7 @@ examples: > compatible = "xlnx,nwl-pcie-2.11"; > reg = <0x0 0xfd0e0000 0x0 0x1000>, > <0x0 0xfd480000 0x0 0x1000>, > - <0x80 0x00000000 0x0 0x1000000>; > + <0x80 0x00000000 0x0 0x10000000>; > reg-names = "breg", "pcireg", "cfg"; > ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, > <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; > -- > 1.8.3.1 >
Our controller is expecting ECAM size to be programmed by software. By
programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB
ECAM region which is used to detect 16 buses, so by updating
"NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB
ECAM region to detect 256 buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
---
changes in v2:
- Update this changes in a seperate patch.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index a73554e..b515019 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_VALUE_DEFAULT 12
+#define NWL_ECAM_VALUE_DEFAULT 16
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
--
1.8.3.1On Tue, Aug 08, 2023 at 04:07:33PM +0530, Thippeswamy Havalige wrote: > Our controller is expecting ECAM size to be programmed by software. By > programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB > ECAM region which is used to detect 16 buses, so by updating > "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB > ECAM region to detect 256 buses. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> 1) I'm still concerned that this adds a revlock with the corresponding DT change. Is that acceptable? Should it be mentioned in the commit log? 2) Lorenzo or Krzysztof, if/when you apply this, please drop the period at the end of the subject line. I've mentioned it several times to no avail. > --- > changes in v2: > - Update this changes in a seperate patch. > --- > drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c > index a73554e..b515019 100644 > --- a/drivers/pci/controller/pcie-xilinx-nwl.c > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c > @@ -126,7 +126,7 @@ > #define E_ECAM_CR_ENABLE BIT(0) > #define E_ECAM_SIZE_LOC GENMASK(20, 16) > #define E_ECAM_SIZE_SHIFT 16 > -#define NWL_ECAM_VALUE_DEFAULT 12 > +#define NWL_ECAM_VALUE_DEFAULT 16 > > #define CFG_DMA_REG_BAR GENMASK(2, 0) > #define CFG_PCIE_CACHE GENMASK(7, 0) > -- > 1.8.3.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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