Current driver is supports up to 16 buses. The following code fixes 
to support up to 256 buses.

update "NWL_ECAM_VALUE_DEFAULT " to 16  can access up to 256MB ECAM
region to detect 256 buses.

Remove redundant code which updates primary,secondary and sub-ordinate
register offset 0x18 in type1 header.

Update ecam size to 256MB in device tree binding example.

Thippeswamy Havalige (2):
  PCI: xilinx-nwl: Update ECAM default value and remove unnecessary    
    code.
  dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example.

 .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml         |  2 +-
 drivers/pci/controller/pcie-xilinx-nwl.c               | 18 +++---------------
 2 files changed, 4 insertions(+), 16 deletions(-)

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1.8.3.1