[v3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap

[PATCH v3 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap

Smita Koralahalli posted 3 patches 2 years, 1 month ago

Diff against v2 v4
Download series mbox

There is a newer version of this series

drivers/cxl/pci.c          | 7 +++----
drivers/pci/pcie/aer.c     | 1 +
drivers/pci/pcie/portdrv.h | 2 --
include/linux/aer.h        | 2 ++
4 files changed, 6 insertions(+), 6 deletions(-)

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[PATCH v3 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap

Posted by Smita Koralahalli 2 years, 1 month ago

This series of patches fixes the appropriate _OSC check for CXL RAS
registers.

First patch addresses the _OSC check.

Second patch moves around pcie_aer_is_native() function declaration to a
common location to be used by cxl/pci module and third patch reuses
pcie_aer_is_native() in cxl/pci module.

Link to v2:
https://lore.kernel.org/all/20230721214740.256602-1-Smita.KoralahalliChannabasappa@amd.com

Smita Koralahalli (3):
  cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS
    registers
  PCI/AER: Export pcie_aer_is_native()
  cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()

 drivers/cxl/pci.c          | 7 +++----
 drivers/pci/pcie/aer.c     | 1 +
 drivers/pci/pcie/portdrv.h | 2 --
 include/linux/aer.h        | 2 ++
 4 files changed, 6 insertions(+), 6 deletions(-)

-- 
2.17.1