On Tue, Aug 01, 2023 at 09:02:31AM +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>
> Add reset ID definitions required for Intel Agilex5 SoCFPGA, re-use
> altr,rst-mgr-s10.h as common header file similar S10 & Agilex.
>
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> ---
> include/dt-bindings/reset/altr,rst-mgr-s10.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
> index 70ea3a09dbe1..04c4d0c6fd34 100644
> --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h
> +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
> @@ -63,12 +63,15 @@
> #define I2C2_RESET 74
> #define I2C3_RESET 75
> #define I2C4_RESET 76
> -/* 77-79 is empty */
> +#define I3C0_RESET 77
> +#define I3C1_RESET 78
> +/* 79 is empty */
> #define UART0_RESET 80
> #define UART1_RESET 81
> /* 82-87 is empty */
> #define GPIO0_RESET 88
> #define GPIO1_RESET 89
> +#define WATCHDOG4_RESET 90
>
> /* BRGMODRST */
> #define SOC2FPGA_RESET 96
> --
> 2.25.1
>