Added dt-binding documentation for Versal NET platforms.

Versal Net is a new AMD/Xilinx  SoC.

The SoC and its architecture is based on the Versal ACAP device.
The Versal Net  device includes more security features in the
platform management controller (PMC) and increases the number
of CPUs in the application processing unit (APU) and the
real-time processing unit (RPU).

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
---
Changes in V2:
- Addressed Krzysztof and Conor review comments:
 - Updated the commit message [1/2] with detail description of Versal NET SoC.
 - Removed the dt-bindings include versal NET header from the binding documents
   as it is not used by the driver.

Link: https://lore.kernel.org/lkml/20230717112348.1381367-1-piyush.mehta@amd.com/ 
---
 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
index 0d50f6a54af3..49db66801429 100644
--- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
@@ -32,6 +32,7 @@ properties:
     enum:
       - xlnx,zynqmp-reset
       - xlnx,versal-reset
+      - xlnx,versal-net-reset
 
   "#reset-cells":
     const: 1
-- 
2.25.1

On 21/07/2023 06:11, Piyush Mehta wrote:
> Added dt-binding documentation for Versal NET platforms.
> 
> Versal Net is a new AMD/Xilinx  SoC.
> 
> The SoC and its architecture is based on the Versal ACAP device.
> The Versal Net  device includes more security features in the
> platform management controller (PMC) and increases the number
> of CPUs in the application processing unit (APU) and the
> real-time processing unit (RPU).
> 
> Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof