Fixes XAUI/RXAUI lane alignment errors.
Issue causes dropped packets when trying to communicate over
fiber via SERDES lanes of port 9 and 10.

Signed-off-by: Ante Knezic <ante.knezic@helmholz.de>
---
 drivers/net/dsa/mv88e6xxx/serdes.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c
index 80167d53212f..a8340b300c92 100644
--- a/drivers/net/dsa/mv88e6xxx/serdes.c
+++ b/drivers/net/dsa/mv88e6xxx/serdes.c
@@ -829,6 +829,37 @@ static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, int lane
 				      MV88E6390_PG_CONTROL, reg);
 }
 
+static int mv88e6390x_serdes_erratum_3_14(struct mv88e6xxx_chip *chip)
+{
+	int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1,
+		MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3,
+		MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1,
+		MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 };
+	int err, i;
+
+	/* 88e6390x-88e6190x errata 3.14:
+	 * After chip reset, SERDES reconfiguration or SERDES core
+	 * Software Reset, the SERDES lanes may not be properly aligned
+	 * resulting in CRC errors
+	 */
+
+	for (i = 0; i < ARRAY_SIZE(lanes); i++) {
+		err = mv88e6390_serdes_write(chip, lanes[i],
+					     MDIO_MMD_PHYXS,
+					     0xf054, 0x400C);
+		if (err)
+			return err;
+
+		err = mv88e6390_serdes_write(chip, lanes[i],
+					     MDIO_MMD_PHYXS,
+					     0xf054, 0x4000);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 			   bool up)
 {
@@ -853,6 +884,12 @@ int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 	if (!err && up)
 		err = mv88e6390_serdes_enable_checker(chip, lane);
 
+	if (!err && up) {
+		if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X ||
+		    chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X)
+			err = mv88e6390x_serdes_erratum_3_14(chip);
+	}
+
 	return err;
 }
 
-- 
2.11.0

> +static int mv88e6390x_serdes_erratum_3_14(struct mv88e6xxx_chip *chip)
> +{
> +	int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1,
> +		MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3,
> +		MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1,
> +		MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 };

Please make this const. Otherwise you end up with two copies of it.

> +	int err, i;
> +
> +	/* 88e6390x-88e6190x errata 3.14:
> +	 * After chip reset, SERDES reconfiguration or SERDES core
> +	 * Software Reset, the SERDES lanes may not be properly aligned
> +	 * resulting in CRC errors
> +	 */
> +
> +	for (i = 0; i < ARRAY_SIZE(lanes); i++) {
> +		err = mv88e6390_serdes_write(chip, lanes[i],
> +					     MDIO_MMD_PHYXS,
> +					     0xf054, 0x400C);

Does Marvell give this register a name? If so, please add a #define.
Are the bits in the register documented?

> +	if (!err && up) {
> +		if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X ||
> +		    chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X)

6191X? 6193X? 

Please sort these into numerical order.


    Andrew

---
pw-bot: cr

>> +static int mv88e6390x_serdes_erratum_3_14(struct mv88e6xxx_chip *chip)
>> +{
>> +     int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1,
>> +             MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3,
>> +             MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1,
>> +             MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 };

>Please make this const. Otherwise you end up with two copies of it.

will do. 

>> +     int err, i;
>> +
>> +     /* 88e6390x-88e6190x errata 3.14:
>> +      * After chip reset, SERDES reconfiguration or SERDES core
>> +      * Software Reset, the SERDES lanes may not be properly aligned
>> +      * resulting in CRC errors
>> +      */
>> +
>> +     for (i = 0; i < ARRAY_SIZE(lanes); i++) {
>> +             err = mv88e6390_serdes_write(chip, lanes[i],
>> +                                          MDIO_MMD_PHYXS,
>> +                                          0xf054, 0x400C);

>Does Marvell give this register a name? If so, please add a #define.
>Are the bits in the register documented?

Unfortunately, no. This is one of those undocumented registers. I will
make a note of it in the commit message.

>> +     if (!err && up) {
>> +             if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X ||
>> +                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X)

>6191X? 6193X?

Errata I have available refers only to 6190x and 6390x. Not sure about other devices.

>Please sort these into numerical order.

will do.

> >Does Marvell give this register a name? If so, please add a #define.
> >Are the bits in the register documented?
> 
> Unfortunately, no. This is one of those undocumented registers. I will
> make a note of it in the commit message.

Undocumented magic is typical for Marvell Erratas.

> 
> >> +     if (!err && up) {
> >> +             if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X ||
> >> +                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X)
> 
> >6191X? 6193X?
> 
> Errata I have available refers only to 6190x and 6390x. Not sure about other devices.

Please mention this in the commit message.

Thanks
	Andrew