drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
support for 256 Byte payload").
Consider a PCIe hierarchy with a PCIe switch and a device connected
downstream of the switch that has support for MPS which is the minimum in
the hierarchy, and root port programmed with an MPS in its DevCtl register
that is greater than the minimum. In this scenario, the default bus
configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
MPS settings in the hierarchy correctly resulting in the device with
support for minimum MPS in the hierarchy receiving the TLPs of size more
than that. Although this can be addressed by appending "pci=pcie_bus_safe"
to the kernel command line, it doesn't seem to be a good idea to always
have this commandline argument even for the basic functionality to work.
Reverting commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256
Byte payload") avoids this requirement and ensures that the basic
functionality of the devices irrespective of the hierarchy and the MPS of
the devices in the hierarchy.
To reap the benefits of having support for higher MPS, optionally, one can
always append the kernel command line with "pci=pcie_bus_perf".
Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Fixed a build issue
V2:
* Addressed review comments from Bjorn
drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4fdadc7b045f..a772faff14b5 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
-
val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
@@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
struct device *dev = pcie->dev;
u32 val;
int ret;
- u16 val_16;
if (pcie->ep_state == EP_STATE_ENABLED)
return;
@@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
-
/* Clear Slot Clock Configuration bit if SRNS configuration */
if (pcie->enable_srns) {
+ u16 val_16;
+
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
PCI_EXP_LNKSTA);
val_16 &= ~PCI_EXP_LNKSTA_SLC;
dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
val_16);
}
-
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
--
2.25.1On Mon, Jun 19, 2023 at 03:56:04PM +0530, Vidya Sagar wrote:
> This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
> support for 256 Byte payload").
>
> Consider a PCIe hierarchy with a PCIe switch and a device connected
> downstream of the switch that has support for MPS which is the minimum in
> the hierarchy, and root port programmed with an MPS in its DevCtl register
> that is greater than the minimum. In this scenario, the default bus
> configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
> MPS settings in the hierarchy correctly resulting in the device with
> support for minimum MPS in the hierarchy receiving the TLPs of size more
> than that. Although this can be addressed by appending "pci=pcie_bus_safe"
> to the kernel command line, it doesn't seem to be a good idea to always
> have this commandline argument even for the basic functionality to work.
I think this has some irrelevant detail (IIUC the problem should
happen even without a switch) and could be more specific (I think the
problem case is RP MPS=256, EP only supports MPS=128).
> Reverting commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256
> Byte payload") avoids this requirement and ensures that the basic
> functionality of the devices irrespective of the hierarchy and the MPS of
> the devices in the hierarchy.
"Ensure" is a transitive verb, so "... ensures that the basic
functionality ..." is missing whatever the object should be.
Maybe something like the following?
After 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
payload"), we set MPS=256 for tegra194 Root Ports.
By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
parameter), Linux configures the MPS of every device to match the
upstream bridge, which is impossible if the Root Port has MPS=256
and a device only supports MPS=128.
This scenario results in uncorrectable Malformed TLP errors if the
Root Port sends TLPs with payloads larger than 128 bytes. These
errors can be avoided by using the "pci=pcie_bus_safe" parameter,
but it doesn't seem to be a good idea to always have this parameter
even for basic functionality to work.
Revert 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
payload") so the Root Ports default to MPS=128, which all devices
support.
If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
to get the benefit of larger MPS settings.
> To reap the benefits of having support for higher MPS, optionally, one can
> always append the kernel command line with "pci=pcie_bus_perf".
>
> Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * Fixed a build issue
>
> V2:
> * Addressed review comments from Bjorn
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4fdadc7b045f..a772faff14b5 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
> val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
> dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
> @@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> struct device *dev = pcie->dev;
> u32 val;
> int ret;
> - u16 val_16;
>
> if (pcie->ep_state == EP_STATE_ENABLED)
> return;
> @@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> + u16 val_16;
> +
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> PCI_EXP_LNKSTA);
> val_16 &= ~PCI_EXP_LNKSTA_SLC;
> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
> val_16);
> }
> -
> clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>
> val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
> --
> 2.25.1
>
On 7/14/2023 3:09 AM, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> On Mon, Jun 19, 2023 at 03:56:04PM +0530, Vidya Sagar wrote:
>> This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
>> support for 256 Byte payload").
>>
>> Consider a PCIe hierarchy with a PCIe switch and a device connected
>> downstream of the switch that has support for MPS which is the minimum in
>> the hierarchy, and root port programmed with an MPS in its DevCtl register
>> that is greater than the minimum. In this scenario, the default bus
>> configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
>> MPS settings in the hierarchy correctly resulting in the device with
>> support for minimum MPS in the hierarchy receiving the TLPs of size more
>> than that. Although this can be addressed by appending "pci=pcie_bus_safe"
>> to the kernel command line, it doesn't seem to be a good idea to always
>> have this commandline argument even for the basic functionality to work.
>
> I think this has some irrelevant detail (IIUC the problem should
> happen even without a switch) and could be more specific (I think the
> problem case is RP MPS=256, EP only supports MPS=128).
The issue is present only if there is a switch.
>
>> Reverting commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256
>> Byte payload") avoids this requirement and ensures that the basic
>> functionality of the devices irrespective of the hierarchy and the MPS of
>> the devices in the hierarchy.
>
> "Ensure" is a transitive verb, so "... ensures that the basic
> functionality ..." is missing whatever the object should be.
I think I missed to add 'work' in the end after 'hierarchy'. My bad.
>
> Maybe something like the following?
>
> After 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload"), we set MPS=256 for tegra194 Root Ports.
>
> By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
> parameter), Linux configures the MPS of every device to match the
> upstream bridge, which is impossible if the Root Port has MPS=256
> and a device only supports MPS=128.
>
> This scenario results in uncorrectable Malformed TLP errors if the
> Root Port sends TLPs with payloads larger than 128 bytes. These
> errors can be avoided by using the "pci=pcie_bus_safe" parameter,
> but it doesn't seem to be a good idea to always have this parameter
> even for basic functionality to work.
>
> Revert 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload") so the Root Ports default to MPS=128, which all devices
> support.
>
> If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
> to get the benefit of larger MPS settings.
Thanks, I'll send a new patch with the above commit message.
>
>> To reap the benefits of having support for higher MPS, optionally, one can
>> always append the kernel command line with "pci=pcie_bus_perf".
>>
>> Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> V3:
>> * Fixed a build issue
>>
>> V2:
>> * Addressed review comments from Bjorn
>>
>> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 4fdadc7b045f..a772faff14b5 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
>> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> PCI_CAP_ID_EXP);
>>
>> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
>> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
>> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
>> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
>> -
>> val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
>> val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
>> dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
>> @@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>> struct device *dev = pcie->dev;
>> u32 val;
>> int ret;
>> - u16 val_16;
>>
>> if (pcie->ep_state == EP_STATE_ENABLED)
>> return;
>> @@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> PCI_CAP_ID_EXP);
>>
>> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
>> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
>> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
>> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
>> -
>> /* Clear Slot Clock Configuration bit if SRNS configuration */
>> if (pcie->enable_srns) {
>> + u16 val_16;
>> +
>> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> PCI_EXP_LNKSTA);
>> val_16 &= ~PCI_EXP_LNKSTA_SLC;
>> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
>> val_16);
>> }
>> -
>> clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>>
>> val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
>> --
>> 2.25.1
>>
On Tue, Jul 18, 2023 at 08:03:47AM +0530, Vidya Sagar wrote:
> On 7/14/2023 3:09 AM, Bjorn Helgaas wrote:
> > On Mon, Jun 19, 2023 at 03:56:04PM +0530, Vidya Sagar wrote:
> > > This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
> > > support for 256 Byte payload").
> > >
> > > Consider a PCIe hierarchy with a PCIe switch and a device connected
> > > downstream of the switch that has support for MPS which is the minimum in
> > > the hierarchy, and root port programmed with an MPS in its DevCtl register
> > > that is greater than the minimum. In this scenario, the default bus
> > > configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
> > > MPS settings in the hierarchy correctly resulting in the device with
> > > support for minimum MPS in the hierarchy receiving the TLPs of size more
> > > than that. Although this can be addressed by appending "pci=pcie_bus_safe"
> > > to the kernel command line, it doesn't seem to be a good idea to always
> > > have this commandline argument even for the basic functionality to work.
> >
> > I think this has some irrelevant detail (IIUC the problem should
> > happen even without a switch) and could be more specific (I think the
> > problem case is RP MPS=256, EP only supports MPS=128).
>
> The issue is present only if there is a switch.
So if there's no switch, and an EP that only supports MPS=128, the PCI
core changes the RP MPS setting to 128? Just based on reading the
code, I thought we would leave RP MPS=256 and EP MPS=128, which would
be a problem. But maybe the PCI core changes the RP down to MPS=128?
Bjorn
On 7/18/2023 4:39 PM, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> On Tue, Jul 18, 2023 at 08:03:47AM +0530, Vidya Sagar wrote:
>> On 7/14/2023 3:09 AM, Bjorn Helgaas wrote:
>>> On Mon, Jun 19, 2023 at 03:56:04PM +0530, Vidya Sagar wrote:
>>>> This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
>>>> support for 256 Byte payload").
>>>>
>>>> Consider a PCIe hierarchy with a PCIe switch and a device connected
>>>> downstream of the switch that has support for MPS which is the minimum in
>>>> the hierarchy, and root port programmed with an MPS in its DevCtl register
>>>> that is greater than the minimum. In this scenario, the default bus
>>>> configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
>>>> MPS settings in the hierarchy correctly resulting in the device with
>>>> support for minimum MPS in the hierarchy receiving the TLPs of size more
>>>> than that. Although this can be addressed by appending "pci=pcie_bus_safe"
>>>> to the kernel command line, it doesn't seem to be a good idea to always
>>>> have this commandline argument even for the basic functionality to work.
>>>
>>> I think this has some irrelevant detail (IIUC the problem should
>>> happen even without a switch) and could be more specific (I think the
>>> problem case is RP MPS=256, EP only supports MPS=128).
>>
>> The issue is present only if there is a switch.
>
> So if there's no switch, and an EP that only supports MPS=128, the PCI
> core changes the RP MPS setting to 128? Just based on reading the
Yes. The code after the if condition here takes care of that.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/probe.c?h=v6.5-rc2#n2049
> code, I thought we would leave RP MPS=256 and EP MPS=128, which would
> be a problem. But maybe the PCI core changes the RP down to MPS=128?
>
> Bjorn
On Wed, Jul 19, 2023 at 04:31:13PM +0530, Vidya Sagar wrote:
> On 7/18/2023 4:39 PM, Bjorn Helgaas wrote:
> > On Tue, Jul 18, 2023 at 08:03:47AM +0530, Vidya Sagar wrote:
> > > On 7/14/2023 3:09 AM, Bjorn Helgaas wrote:
> > > > On Mon, Jun 19, 2023 at 03:56:04PM +0530, Vidya Sagar wrote:
> > > > > This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
> > > > > support for 256 Byte payload").
> > > > >
> > > > > Consider a PCIe hierarchy with a PCIe switch and a device connected
> > > > > downstream of the switch that has support for MPS which is the minimum in
> > > > > the hierarchy, and root port programmed with an MPS in its DevCtl register
> > > > > that is greater than the minimum. In this scenario, the default bus
> > > > > configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
> > > > > MPS settings in the hierarchy correctly resulting in the device with
> > > > > support for minimum MPS in the hierarchy receiving the TLPs of size more
> > > > > than that. Although this can be addressed by appending "pci=pcie_bus_safe"
> > > > > to the kernel command line, it doesn't seem to be a good idea to always
> > > > > have this commandline argument even for the basic functionality to work.
> > > >
> > > > I think this has some irrelevant detail (IIUC the problem should
> > > > happen even without a switch) and could be more specific (I think the
> > > > problem case is RP MPS=256, EP only supports MPS=128).
> > >
> > > The issue is present only if there is a switch.
> >
> > So if there's no switch, and an EP that only supports MPS=128, the PCI
> > core changes the RP MPS setting to 128? Just based on reading the
>
> Yes. The code after the if condition here takes care of that.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/probe.c?h=v6.5-rc2#n2049
Oh, right, thanks. I vaguely remember the logic that if the immediate
parent is a Root Port, there are no other branches in the hierarchy to
worry about, so we can just configure the Root Port MPS to match the
device.
> > code, I thought we would leave RP MPS=256 and EP MPS=128, which would
> > be a problem. But maybe the PCI core changes the RP down to MPS=128?
> >
> > Bjorn
Hello,
> This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable
> support for 256 Byte payload").
>
> Consider a PCIe hierarchy with a PCIe switch and a device connected
> downstream of the switch that has support for MPS which is the minimum in
> the hierarchy, and root port programmed with an MPS in its DevCtl register
> that is greater than the minimum. In this scenario, the default bus
> configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the
> MPS settings in the hierarchy correctly resulting in the device with
> support for minimum MPS in the hierarchy receiving the TLPs of size more
> than that. Although this can be addressed by appending "pci=pcie_bus_safe"
> to the kernel command line, it doesn't seem to be a good idea to always
> have this commandline argument even for the basic functionality to work.
>
> Reverting commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256
> Byte payload") avoids this requirement and ensures that the basic
> functionality of the devices irrespective of the hierarchy and the MPS of
> the devices in the hierarchy.
>
> To reap the benefits of having support for higher MPS, optionally, one can
> always append the kernel command line with "pci=pcie_bus_perf".
Applied to controller/tegra194, thank you!
[1/1] Revert "PCI: tegra194: Enable support for 256 Byte payload"
https://git.kernel.org/pci/pci/c/606295f16360
Krzysztof
After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
payload"), we set MPS=256 for tegra194 Root Ports.
By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
parameter), Linux configures the MPS of every device to match the
upstream bridge, which is impossible if the Root Port has MPS=256
and a device only supports MPS=128.
This scenario results in uncorrectable Malformed TLP errors if the
Root Port sends TLPs with payloads larger than 128 bytes. These
errors can be avoided by using the "pci=pcie_bus_safe" parameter,
but it doesn't seem to be a good idea to always have this parameter
even for basic functionality to work.
Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
payload") so the Root Ports default to MPS=128, which all devices
support.
If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
to get the benefit of larger MPS settings.
[ rewrote commit message based on Bjorn's suggestion ]
Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V4:
* Rewrote commit message based on Bjorn's suggestion
V3:
* Fixed a build issue
V2:
* Addressed review comments from Bjorn
drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4fdadc7b045f..a772faff14b5 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
-
val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
@@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
struct device *dev = pcie->dev;
u32 val;
int ret;
- u16 val_16;
if (pcie->ep_state == EP_STATE_ENABLED)
return;
@@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
-
/* Clear Slot Clock Configuration bit if SRNS configuration */
if (pcie->enable_srns) {
+ u16 val_16;
+
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
PCI_EXP_LNKSTA);
val_16 &= ~PCI_EXP_LNKSTA_SLC;
dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
val_16);
}
-
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
--
2.25.1On Tue, Jul 18, 2023 at 08:22:21AM +0530, Vidya Sagar wrote:
> After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload"), we set MPS=256 for tegra194 Root Ports.
>
> By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
> parameter), Linux configures the MPS of every device to match the
> upstream bridge, which is impossible if the Root Port has MPS=256
> and a device only supports MPS=128.
Thanks for pointing out that I broke this log by omitting the mention
of a switch. Is the rewording below better? If so, Krzysztof can
amend the commit.
After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
payload"), we initialize MPS=256 for tegra194 Root Ports before enumerating
the hierarchy.
Consider an Endpoint that supports only MPS=128. In the default situation
(CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*" parameter), Linux
tries to configure the MPS of every device to match the upstream bridge.
If the Endpoint is directly below the Root Port, Linux can reduce the Root
Port MPS to 128 to match the Endpoint. But if there's a switch in the
middle, Linux doesn't reduce the Root Port MPS because other devices below
the switch may already be configured with MPS larger than 128.
> This scenario results in uncorrectable Malformed TLP errors if the
> Root Port sends TLPs with payloads larger than 128 bytes. These
> errors can be avoided by using the "pci=pcie_bus_safe" parameter,
> but it doesn't seem to be a good idea to always have this parameter
> even for basic functionality to work.
>
> Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload") so the Root Ports default to MPS=128, which all devices
> support.
>
> If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
> to get the benefit of larger MPS settings.
>
> [ rewrote commit message based on Bjorn's suggestion ]
>
> Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
4fb8e46c1bc4 appeared in v6.0-rc1, so this wouldn't be a candidate for
v6.5, but it does sound like it should be tagged for stable? If so,
Krzysztof can probably add that as well.
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V4:
> * Rewrote commit message based on Bjorn's suggestion
>
> V3:
> * Fixed a build issue
>
> V2:
> * Addressed review comments from Bjorn
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4fdadc7b045f..a772faff14b5 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
> val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
> dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
> @@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> struct device *dev = pcie->dev;
> u32 val;
> int ret;
> - u16 val_16;
>
> if (pcie->ep_state == EP_STATE_ENABLED)
> return;
> @@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> + u16 val_16;
> +
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> PCI_EXP_LNKSTA);
> val_16 &= ~PCI_EXP_LNKSTA_SLC;
> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
> val_16);
> }
> -
> clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>
> val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
> --
> 2.25.1
>
On 8/2/2023 2:10 AM, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> On Tue, Jul 18, 2023 at 08:22:21AM +0530, Vidya Sagar wrote:
>> After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
>> payload"), we set MPS=256 for tegra194 Root Ports.
>>
>> By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
>> parameter), Linux configures the MPS of every device to match the
>> upstream bridge, which is impossible if the Root Port has MPS=256
>> and a device only supports MPS=128.
>
> Thanks for pointing out that I broke this log by omitting the mention
> of a switch. Is the rewording below better? If so, Krzysztof can
> amend the commit.
Yes. The below rewording looks good.
Thanks,
Vidya Sagar
>
> After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload"), we initialize MPS=256 for tegra194 Root Ports before enumerating
> the hierarchy.
>
> Consider an Endpoint that supports only MPS=128. In the default situation
> (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*" parameter), Linux
> tries to configure the MPS of every device to match the upstream bridge.
> If the Endpoint is directly below the Root Port, Linux can reduce the Root
> Port MPS to 128 to match the Endpoint. But if there's a switch in the
> middle, Linux doesn't reduce the Root Port MPS because other devices below
> the switch may already be configured with MPS larger than 128.
>
>> This scenario results in uncorrectable Malformed TLP errors if the
>> Root Port sends TLPs with payloads larger than 128 bytes. These
>> errors can be avoided by using the "pci=pcie_bus_safe" parameter,
>> but it doesn't seem to be a good idea to always have this parameter
>> even for basic functionality to work.
>>
>> Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
>> payload") so the Root Ports default to MPS=128, which all devices
>> support.
>>
>> If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
>> to get the benefit of larger MPS settings.
>>
>> [ rewrote commit message based on Bjorn's suggestion ]
>>
>> Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
>
> 4fb8e46c1bc4 appeared in v6.0-rc1, so this wouldn't be a candidate for
> v6.5, but it does sound like it should be tagged for stable? If so,
> Krzysztof can probably add that as well.
>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> V4:
>> * Rewrote commit message based on Bjorn's suggestion
>>
>> V3:
>> * Fixed a build issue
>>
>> V2:
>> * Addressed review comments from Bjorn
>>
>> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 4fdadc7b045f..a772faff14b5 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
>> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> PCI_CAP_ID_EXP);
>>
>> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
>> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
>> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
>> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
>> -
>> val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
>> val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
>> dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
>> @@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>> struct device *dev = pcie->dev;
>> u32 val;
>> int ret;
>> - u16 val_16;
>>
>> if (pcie->ep_state == EP_STATE_ENABLED)
>> return;
>> @@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> PCI_CAP_ID_EXP);
>>
>> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
>> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
>> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
>> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
>> -
>> /* Clear Slot Clock Configuration bit if SRNS configuration */
>> if (pcie->enable_srns) {
>> + u16 val_16;
>> +
>> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> PCI_EXP_LNKSTA);
>> val_16 &= ~PCI_EXP_LNKSTA_SLC;
>> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
>> val_16);
>> }
>> -
>> clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>>
>> val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
>> --
>> 2.25.1
>>
Hello!
[...]
> > > After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> > > payload"), we set MPS=256 for tegra194 Root Ports.
> > >
> > > By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
> > > parameter), Linux configures the MPS of every device to match the
> > > upstream bridge, which is impossible if the Root Port has MPS=256
> > > and a device only supports MPS=128.
> >
> > Thanks for pointing out that I broke this log by omitting the mention
> > of a switch. Is the rewording below better? If so, Krzysztof can
> > amend the commit.
> Yes. The below rewording looks good.
Updated commit at:
https://git.kernel.org/pci/pci/c/ebfde1584d9f
Thank you everyone!
Krzysztof
Hi Krzysztof, Bjorn,
On 18/07/2023 03:52, Vidya Sagar wrote:
> After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload"), we set MPS=256 for tegra194 Root Ports.
>
> By default (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*"
> parameter), Linux configures the MPS of every device to match the
> upstream bridge, which is impossible if the Root Port has MPS=256
> and a device only supports MPS=128.
>
> This scenario results in uncorrectable Malformed TLP errors if the
> Root Port sends TLPs with payloads larger than 128 bytes. These
> errors can be avoided by using the "pci=pcie_bus_safe" parameter,
> but it doesn't seem to be a good idea to always have this parameter
> even for basic functionality to work.
>
> Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
> payload") so the Root Ports default to MPS=128, which all devices
> support.
>
> If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf"
> to get the benefit of larger MPS settings.
>
> [ rewrote commit message based on Bjorn's suggestion ]
>
> Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V4:
> * Rewrote commit message based on Bjorn's suggestion
>
> V3:
> * Fixed a build issue
>
> V2:
> * Addressed review comments from Bjorn
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4fdadc7b045f..a772faff14b5 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -900,11 +900,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
> val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
> dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
> @@ -1756,7 +1751,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> struct device *dev = pcie->dev;
> u32 val;
> int ret;
> - u16 val_16;
>
> if (pcie->ep_state == EP_STATE_ENABLED)
> return;
> @@ -1887,20 +1881,16 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
> pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
> PCI_CAP_ID_EXP);
>
> - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
> - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
> - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
> -
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> + u16 val_16;
> +
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> PCI_EXP_LNKSTA);
> val_16 &= ~PCI_EXP_LNKSTA_SLC;
> dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
> val_16);
> }
> -
> clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>
> val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
I see a version of this patch here ...
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/tegra194
However, I don't see this in -next yet. If you are happy with this
latest version, could we get this into -next?
FWIW ...
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Thanks!
Jon
--
nvpublic
On Fri, Jul 21, 2023 at 09:23:01AM +0100, Jon Hunter wrote: > ... > I see a version of this patch here ... > > https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/tegra194 > > However, I don't see this in -next yet. If you are happy with this latest > version, could we get this into -next? I'm on vacation until Tuesday; will build a new -next branch Tuesday or Wednesday.
Hi Bjorn, On 21/07/2023 11:35, Bjorn Helgaas wrote: > On Fri, Jul 21, 2023 at 09:23:01AM +0100, Jon Hunter wrote: >> ... > >> I see a version of this patch here ... >> >> https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/tegra194 >> >> However, I don't see this in -next yet. If you are happy with this latest >> version, could we get this into -next? > > I'm on vacation until Tuesday; will build a new -next branch Tuesday > or Wednesday. A friendly reminder on this. Can we queue this up for -next? I know that there is further discussion on-going about if the core could handle this, but right now PCIe is broken on our NVIDIA IGX Orin board and we would like to merge this now in the short-term at least. Thanks! Jon -- nvpublic
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