Add MT8188 VDO1 reset bit map.
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 3 +-
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index c3e3c5cfe931..208d4dfedc1a 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
[MT8188_VDO0_RST_DISP_RSZ0] = 31,
};
+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+ [MT8188_VDO1_RST_SMI_LARB2] = 0,
+ [MT8188_VDO1_RST_SMI_LARB3] = 1,
+ [MT8188_VDO1_RST_GALS] = 2,
+ [MT8188_VDO1_RST_FAKE_ENG0] = 3,
+ [MT8188_VDO1_RST_FAKE_ENG1] = 4,
+ [MT8188_VDO1_RST_MDP_RDMA0] = 5,
+ [MT8188_VDO1_RST_MDP_RDMA1] = 6,
+ [MT8188_VDO1_RST_MDP_RDMA2] = 7,
+ [MT8188_VDO1_RST_MDP_RDMA3] = 8,
+ [MT8188_VDO1_RST_VPP_MERGE0] = 9,
+ [MT8188_VDO1_RST_VPP_MERGE1] = 10,
+ [MT8188_VDO1_RST_VPP_MERGE2] = 11,
+ [MT8188_VDO1_RST_VPP_MERGE3] = 32 + 0,
+ [MT8188_VDO1_RST_VPP_MERGE4] = 32 + 1,
+ [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = 32 + 2,
+ [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = 32 + 3,
+ [MT8188_VDO1_RST_DISP_MUTEX] = 32 + 4,
+ [MT8188_VDO1_RST_MDP_RDMA4] = 32 + 5,
+ [MT8188_VDO1_RST_MDP_RDMA5] = 32 + 6,
+ [MT8188_VDO1_RST_MDP_RDMA6] = 32 + 7,
+ [MT8188_VDO1_RST_MDP_RDMA7] = 32 + 8,
+ [MT8188_VDO1_RST_DP_INTF1_MMCK] = 32 + 9,
+ [MT8188_VDO1_RST_DPI0_MM_CK] = 32 + 10,
+ [MT8188_VDO1_RST_DPI1_MM_CK] = 32 + 11,
+ [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = 32 + 13,
+ [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = 32 + 14,
+ [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = 32 + 15,
+ [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = 32 + 16,
+ [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = 32 + 17,
+ [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = 32 + 18,
+ [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = 32 + 19,
+ [MT8188_VDO1_RST_PADDING0] = 32 + 20,
+ [MT8188_VDO1_RST_PADDING1] = 32 + 21,
+ [MT8188_VDO1_RST_PADDING2] = 32 + 22,
+ [MT8188_VDO1_RST_PADDING3] = 32 + 23,
+ [MT8188_VDO1_RST_PADDING4] = 32 + 24,
+ [MT8188_VDO1_RST_PADDING5] = 32 + 25,
+ [MT8188_VDO1_RST_PADDING6] = 32 + 26,
+ [MT8188_VDO1_RST_PADDING7] = 32 + 27,
+ [MT8188_VDO1_RST_DISP_RSZ0] = 32 + 28,
+ [MT8188_VDO1_RST_DISP_RSZ1] = 32 + 29,
+ [MT8188_VDO1_RST_DISP_RSZ2] = 32 + 30,
+ [MT8188_VDO1_RST_DISP_RSZ3] = 32 + 31,
+ [MT8188_VDO1_RST_HDR_VDO_FE0] = 64 + 0,
+ [MT8188_VDO1_RST_HDR_GFX_FE0] = 64 + 1,
+ [MT8188_VDO1_RST_HDR_VDO_BE] = 64 + 2,
+ [MT8188_VDO1_RST_HDR_VDO_FE1] = 64 + 16,
+ [MT8188_VDO1_RST_HDR_GFX_FE1] = 64 + 17,
+ [MT8188_VDO1_RST_DISP_MIXER] = 64 + 18,
+ [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = 64 + 19,
+ [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = 64 + 20,
+ [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = 64 + 21,
+ [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = 64 + 22,
+ [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = 64 + 23,
+};
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 88029500ed4d..7a6221f87669 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -97,7 +97,8 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
.routes = mmsys_mt8188_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
- .num_resets = 96,
+ .rst_tb = mmsys_mt8188_vdo1_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
.vsync_len = 1,
};
--
2.18.0Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO1 reset bit map.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 3 +-
> 2 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index c3e3c5cfe931..208d4dfedc1a 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
> [MT8188_VDO0_RST_DISP_RSZ0] = 31,
> };
>
> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> + [MT8188_VDO1_RST_SMI_LARB2] = 0,
> + [MT8188_VDO1_RST_SMI_LARB3] = 1,
> + [MT8188_VDO1_RST_GALS] = 2,
> + [MT8188_VDO1_RST_FAKE_ENG0] = 3,
> + [MT8188_VDO1_RST_FAKE_ENG1] = 4,
> + [MT8188_VDO1_RST_MDP_RDMA0] = 5,
> + [MT8188_VDO1_RST_MDP_RDMA1] = 6,
> + [MT8188_VDO1_RST_MDP_RDMA2] = 7,
> + [MT8188_VDO1_RST_MDP_RDMA3] = 8,
> + [MT8188_VDO1_RST_VPP_MERGE0] = 9,
> + [MT8188_VDO1_RST_VPP_MERGE1] = 10,
> + [MT8188_VDO1_RST_VPP_MERGE2] = 11,
> + [MT8188_VDO1_RST_VPP_MERGE3] = 32 + 0,
Works, but there's a better way.
32 + 0 means that you're using reset SW1 register, so you can do
#define MT8188_MMSYS_RST_NR_PER_BANK 32
#define MT8188_RST_SW1_OFFSET MT8188_MMSYS_RST_NR_PER_BANK
#define MT8188_RST_SW2_OFFSET MT8188_MMSYS_RST_NR_PER_BANK * 2
[MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
[MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
.......
[MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
...etc
Reading this will make it clear that a certain reset bit is in a different
(sequential or not) register.
P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all reset registers
for all SoCs are always 32 bits, which I believe is true), you could move that
definition to mtk-mmsys.h as
#define MMSYS_RST_NR_PER_BANK 32
and then define the offsets in mt8188-mmsys.h as
#define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
.... etc
Thanks,
Angelo
Hi Angelo,
Got it. Will fix this in the next version.
Added a new define in mtk-mmsys.h:
#define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)
And define the reset table as:
static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
[MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
...
[MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
[MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
...
[MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31),
[MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
...
[MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
};
Thanks,
Hsiao Chien Sung
On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > Add MT8188 VDO1 reset bit map.
> >
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8188-mmsys.h | 57
> +++++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 3 +-
> > 2 files changed, 59 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
> b/drivers/soc/mediatek/mt8188-mmsys.h
> > index c3e3c5cfe931..208d4dfedc1a 100644
> > --- a/drivers/soc/mediatek/mt8188-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> > @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
> > [MT8188_VDO0_RST_DISP_RSZ0]= 31,
> > };
> >
> > +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> > +[MT8188_VDO1_RST_SMI_LARB2]= 0,
> > +[MT8188_VDO1_RST_SMI_LARB3]= 1,
> > +[MT8188_VDO1_RST_GALS]= 2,
> > +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
> > +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
> > +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
> > +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
> > +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
> > +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
> > +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
> > +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
> > +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
> > +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
>
> Works, but there's a better way.
>
> 32 + 0 means that you're using reset SW1 register, so you can do
>
> #define MT8188_MMSYS_RST_NR_PER_BANK32
> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
>
> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
> .......
> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
> ...etc
>
> Reading this will make it clear that a certain reset bit is in a
> different
> (sequential or not) register.
>
> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
> reset registers
> for all SoCs are always 32 bits, which I believe is true), you could
> move that
> definition to mtk-mmsys.h as
> #define MMSYS_RST_NR_PER_BANK32
> and then define the offsets in mt8188-mmsys.h as
> #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
> .... etc
>
> Thanks,
> Angelo
>
>
Il 15/06/23 08:01, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
>
> Got it. Will fix this in the next version.
>
> Added a new define in mtk-mmsys.h:
> #define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)
>
> And define the reset table as:
> static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
> ...
> [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
> [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
> ...
> [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31),
> [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
>
> ...
> [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
> };
>
Okay, that's also good. Go on!
Regards,
Angelo
> Thanks,
> Hsiao Chien Sung
>
> On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>>
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>> Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add MT8188 VDO1 reset bit map.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>> ---
>>> drivers/soc/mediatek/mt8188-mmsys.h | 57
>> +++++++++++++++++++++++++++++
>>> drivers/soc/mediatek/mtk-mmsys.c | 3 +-
>>> 2 files changed, 59 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index c3e3c5cfe931..208d4dfedc1a 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>>> [MT8188_VDO0_RST_DISP_RSZ0]= 31,
>>> };
>>>
>>> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>>> +[MT8188_VDO1_RST_SMI_LARB2]= 0,
>>> +[MT8188_VDO1_RST_SMI_LARB3]= 1,
>>> +[MT8188_VDO1_RST_GALS]= 2,
>>> +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
>>> +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
>>> +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
>>> +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
>>> +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
>>> +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
>>> +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
>>> +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
>>> +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
>>> +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
>>
>> Works, but there's a better way.
>>
>> 32 + 0 means that you're using reset SW1 register, so you can do
>>
>> #define MT8188_MMSYS_RST_NR_PER_BANK32
>> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
>> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
>>
>> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
>> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
>> .......
>> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
>> ...etc
>>
>> Reading this will make it clear that a certain reset bit is in a
>> different
>> (sequential or not) register.
>>
>> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
>> reset registers
>> for all SoCs are always 32 bits, which I believe is true), you could
>> move that
>> definition to mtk-mmsys.h as
>> #define MMSYS_RST_NR_PER_BANK32
>> and then define the offsets in mt8188-mmsys.h as
>> #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>> .... etc
>>
>> Thanks,
>> Angelo
>>
>>
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