AMD cpus does not contain hybrid cores. Also, perf mem/c2c on AMD
internally uses IBS OP PMU, not the core PMU.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
 tools/perf/arch/x86/util/pmu.c | 15 +++++++++++++++
 tools/perf/util/pmus.c         |  2 +-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c
index 3c0de3370d7e..8a20d28d9927 100644
--- a/tools/perf/arch/x86/util/pmu.c
+++ b/tools/perf/arch/x86/util/pmu.c
@@ -14,6 +14,8 @@
 #include "../../../util/intel-bts.h"
 #include "../../../util/pmu.h"
 #include "../../../util/fncache.h"
+#include "../../../util/pmus.h"
+#include "env.h"
 
 struct pmu_alias {
 	char *name;
@@ -168,3 +170,16 @@ char *pmu_find_alias_name(const char *name)
 
 	return __pmu_find_alias_name(name);
 }
+
+int perf_pmus__num_mem_pmus(void)
+{
+	/*
+	 * AMD does not have hybrid cores and also uses IBS OP
+	 * pmu for perf mem/c2c.
+	 */
+	if (x86__is_amd_cpu())
+		return 1;
+
+	/* Intel uses core pmus for perf mem/c2c */
+	return perf_pmus__num_core_pmus();
+}
diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c
index e505d2fef828..0ed943932945 100644
--- a/tools/perf/util/pmus.c
+++ b/tools/perf/util/pmus.c
@@ -240,7 +240,7 @@ const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str)
 	return NULL;
 }
 
-int perf_pmus__num_mem_pmus(void)
+int __weak perf_pmus__num_mem_pmus(void)
 {
 	/* All core PMUs are for mem events. */
 	return perf_pmus__num_core_pmus();
-- 
2.40.1

On Tue, Jun 13, 2023 at 2:56 AM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>
> AMD cpus does not contain hybrid cores. Also, perf mem/c2c on AMD
> internally uses IBS OP PMU, not the core PMU.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
>  tools/perf/arch/x86/util/pmu.c | 15 +++++++++++++++
>  tools/perf/util/pmus.c         |  2 +-
>  2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c
> index 3c0de3370d7e..8a20d28d9927 100644
> --- a/tools/perf/arch/x86/util/pmu.c
> +++ b/tools/perf/arch/x86/util/pmu.c
> @@ -14,6 +14,8 @@
>  #include "../../../util/intel-bts.h"
>  #include "../../../util/pmu.h"
>  #include "../../../util/fncache.h"
> +#include "../../../util/pmus.h"
> +#include "env.h"
>
>  struct pmu_alias {
>         char *name;
> @@ -168,3 +170,16 @@ char *pmu_find_alias_name(const char *name)
>
>         return __pmu_find_alias_name(name);
>  }
> +
> +int perf_pmus__num_mem_pmus(void)
> +{
> +       /*
> +        * AMD does not have hybrid cores and also uses IBS OP
> +        * pmu for perf mem/c2c.
> +        */
> +       if (x86__is_amd_cpu())
> +               return 1;

The code and comment seem out of sync here. For the hybrid part
perf_pmus__num_core_pmus() will yield 1 if there is no hybrid, so we
can just use perf_pmus__num_core_pmus(). For the IBS OP part, does
that mean that AMD should have 2 mem pmus? Or is IBS OP a core PMU?
Can we add this as an example in the core/other documentation in patch
1, as you've done for ARM, for clarity.

Thanks,
Ian

> +
> +       /* Intel uses core pmus for perf mem/c2c */
> +       return perf_pmus__num_core_pmus();
> +}
> diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c
> index e505d2fef828..0ed943932945 100644
> --- a/tools/perf/util/pmus.c
> +++ b/tools/perf/util/pmus.c
> @@ -240,7 +240,7 @@ const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str)
>         return NULL;
>  }
>
> -int perf_pmus__num_mem_pmus(void)
> +int __weak perf_pmus__num_mem_pmus(void)
>  {
>         /* All core PMUs are for mem events. */
>         return perf_pmus__num_core_pmus();
> --
> 2.40.1
>

>> +int perf_pmus__num_mem_pmus(void)
>> +{
>> +       /*
>> +        * AMD does not have hybrid cores and also uses IBS OP
>> +        * pmu for perf mem/c2c.
>> +        */
>> +       if (x86__is_amd_cpu())
>> +               return 1;
> 
> The code and comment seem out of sync here. For the hybrid part
> perf_pmus__num_core_pmus() will yield 1 if there is no hybrid, so we
> can just use perf_pmus__num_core_pmus(). For the IBS OP part, does
> that mean that AMD should have 2 mem pmus? Or is IBS OP a core PMU?

Sure. Let me remove hybrid part from the comment.

There are two IBS pmus: ibs_fetch// and ibs_op//. Both of them are
independent of the core pmu (cpu//). An instance of all 3 pmus is
present in each hw SMT thread. And, perf mem/c2c internally uses
ibs_op// pmu on AMD. See tools/perf/arch/x86/util/mem-events.c

  static struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = {
          E(NULL,         NULL,           NULL),
          E(NULL,         NULL,           NULL),
          E("mem-ldst",   "ibs_op//",     "ibs_op"),
  };

Hope this clarifies.

> Can we add this as an example in the core/other documentation in patch
> 1, as you've done for ARM, for clarity.

Sure. Let me also add IBS example in the patch #1 comment.

Thanks,
Ravi