Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index db5253a2a74a..8a56473cdd5a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,7 +61,7 @@ properties:
hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
- $ref: "/schemas/types.yaml#/definitions/string"
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- riscv,sv32
- riscv,sv39
@@ -95,7 +95,7 @@ properties:
While the isa strings in ISA specification are case
insensitive, letters in the riscv,isa string must be all
lowercase.
- $ref: "/schemas/types.yaml#/definitions/string"
+ $ref: /schemas/types.yaml#/definitions/string
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
@@ -120,7 +120,7 @@ properties:
- interrupt-controller
cpu-idle-states:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
--
2.34.1
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Fri, 9 Jun 2023 16:07:06 +0200 you wrote:
> Cleanup bindings dropping unneeded quotes. Once all these are fixed,
> checking for this can be enabled in yamllint.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Here is the summary with links:
- dt-bindings: riscv: cpus: drop unneeded quotes
https://git.kernel.org/riscv/c/f20233852ae2
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
On Fri, 09 Jun 2023 16:07:06 +0200, Krzysztof Kozlowski wrote:
> Cleanup bindings dropping unneeded quotes. Once all these are fixed,
> checking for this can be enabled in yamllint.
>
>
Applied, thanks!
[1/1] dt-bindings: riscv: cpus: drop unneeded quotes
https://git.kernel.org/palmer/c/f20233852ae2
Best regards,
--
Palmer Dabbelt <palmer@rivosinc.com>
On Fri, Jun 9, 2023 at 8:07 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > Cleanup bindings dropping unneeded quotes. Once all these are fixed, > checking for this can be enabled in yamllint. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Note that I already have the whole tree done. Just not all split up. Acked-by: Rob Herring <robh@kernel.org> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index db5253a2a74a..8a56473cdd5a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -61,7 +61,7 @@ properties: > hart. These values originate from the RISC-V Privileged > Specification document, available from > https://riscv.org/specifications/ > - $ref: "/schemas/types.yaml#/definitions/string" > + $ref: /schemas/types.yaml#/definitions/string > enum: > - riscv,sv32 > - riscv,sv39 > @@ -95,7 +95,7 @@ properties: > While the isa strings in ISA specification are case > insensitive, letters in the riscv,isa string must be all > lowercase. > - $ref: "/schemas/types.yaml#/definitions/string" > + $ref: /schemas/types.yaml#/definitions/string > pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > @@ -120,7 +120,7 @@ properties: > - interrupt-controller > > cpu-idle-states: > - $ref: '/schemas/types.yaml#/definitions/phandle-array' > + $ref: /schemas/types.yaml#/definitions/phandle-array > items: > maxItems: 1 > description: | > -- > 2.34.1 >
On 09/06/2023 16:34, Rob Herring wrote: > On Fri, Jun 9, 2023 at 8:07 AM Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> Cleanup bindings dropping unneeded quotes. Once all these are fixed, >> checking for this can be enabled in yamllint. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) > > Note that I already have the whole tree done. Just not all split up. > > Acked-by: Rob Herring <robh@kernel.org> This was on latest next, so I assumed all your patches are already there and few of them are missing. Best regards, Krzysztof
On Fri, Jun 09, 2023 at 04:07:06PM +0200, Krzysztof Kozlowski wrote: > Cleanup bindings dropping unneeded quotes. Once all these are fixed, > checking for this can be enabled in yamllint. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Fri, 09 Jun 2023 07:21:17 PDT (-0700), Conor Dooley wrote: > On Fri, Jun 09, 2023 at 04:07:06PM +0200, Krzysztof Kozlowski wrote: >> Cleanup bindings dropping unneeded quotes. Once all these are fixed, >> checking for this can be enabled in yamllint. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Did you want me to pick this up in the RISC-V tree, or is it aimed somewhere else? > > Thanks, > Conor.
On Wed, Jun 14, 2023 at 07:46:12AM -0700, Palmer Dabbelt wrote: > On Fri, 09 Jun 2023 07:21:17 PDT (-0700), Conor Dooley wrote: > > On Fri, Jun 09, 2023 at 04:07:06PM +0200, Krzysztof Kozlowski wrote: > > > Cleanup bindings dropping unneeded quotes. Once all these are fixed, > > > checking for this can be enabled in yamllint. > > > > > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Did you want me to pick this up in the RISC-V tree, or is it aimed somewhere > else? Usually subsystem, or in this case arch, maintainers should take the bindings patches. So that'd be you ;)
On Wed, 14 Jun 2023 08:03:18 PDT (-0700), Conor Dooley wrote: > On Wed, Jun 14, 2023 at 07:46:12AM -0700, Palmer Dabbelt wrote: >> On Fri, 09 Jun 2023 07:21:17 PDT (-0700), Conor Dooley wrote: >> > On Fri, Jun 09, 2023 at 04:07:06PM +0200, Krzysztof Kozlowski wrote: >> > > Cleanup bindings dropping unneeded quotes. Once all these are fixed, >> > > checking for this can be enabled in yamllint. >> > > >> > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> > >> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> >> >> Did you want me to pick this up in the RISC-V tree, or is it aimed somewhere >> else? > > Usually subsystem, or in this case arch, maintainers should take the > bindings patches. So that'd be you ;) Cool, it's queued up. I'm just put a bunch of stuff in the queue and I think something's failing so it might take a bit to make for-next.
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