The hardware monitoring points for instruction fetching and
load/store operations need to align 4 bytes or 1/2/4/8 bytes respectively.

Reported-by: Colin King <colin.i.king@gmail.com>
Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
---
 arch/loongarch/kernel/hw_breakpoint.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/loongarch/kernel/hw_breakpoint.c b/arch/loongarch/kernel/hw_breakpoint.c
index 2406c95b34cc..021b59c248fa 100644
--- a/arch/loongarch/kernel/hw_breakpoint.c
+++ b/arch/loongarch/kernel/hw_breakpoint.c
@@ -396,6 +396,8 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
 
 	if (hw->ctrl.type != LOONGARCH_BREAKPOINT_EXECUTE)
 		alignment_mask = 0x7;
+	else
+		alignment_mask = 0x3;
 	offset = hw->address & alignment_mask;
 
 	hw->address &= ~alignment_mask;
-- 
2.20.1

Queued, thanks.

Huacai

On Thu, Jun 8, 2023 at 9:02 PM Qing Zhang <zhangqing@loongson.cn> wrote:
>
> The hardware monitoring points for instruction fetching and
> load/store operations need to align 4 bytes or 1/2/4/8 bytes respectively.
>
> Reported-by: Colin King <colin.i.king@gmail.com>
> Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
> ---
>  arch/loongarch/kernel/hw_breakpoint.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/loongarch/kernel/hw_breakpoint.c b/arch/loongarch/kernel/hw_breakpoint.c
> index 2406c95b34cc..021b59c248fa 100644
> --- a/arch/loongarch/kernel/hw_breakpoint.c
> +++ b/arch/loongarch/kernel/hw_breakpoint.c
> @@ -396,6 +396,8 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
>
>         if (hw->ctrl.type != LOONGARCH_BREAKPOINT_EXECUTE)
>                 alignment_mask = 0x7;
> +       else
> +               alignment_mask = 0x3;
>         offset = hw->address & alignment_mask;
>
>         hw->address &= ~alignment_mask;
> --
> 2.20.1
>
>