Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
adapted to the new upstream opp-supported-hw binning format. Also add
dynamic-power-coefficient for the GPU.
Also add label for mfg1 power domain. This is to be used at the board
level to add a regulator supply for the power domain.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c58d7eb87b1d..a34489e27cd4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -695,6 +695,142 @@ clk32k: oscillator-32k {
clock-output-names = "clk32k";
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-299000000 {
+ opp-hz = /bits/ 64 <299000000>;
+ opp-microvolt = <612500>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-332000000 {
+ opp-hz = /bits/ 64 <332000000>;
+ opp-microvolt = <625000>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ opp-microvolt = <637500>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <643750>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-434000000 {
+ opp-hz = /bits/ 64 <434000000>;
+ opp-microvolt = <656250>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-484000000 {
+ opp-hz = /bits/ 64 <484000000>;
+ opp-microvolt = <668750>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-535000000 {
+ opp-hz = /bits/ 64 <535000000>;
+ opp-microvolt = <687500>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-586000000 {
+ opp-hz = /bits/ 64 <586000000>;
+ opp-microvolt = <700000>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-637000000 {
+ opp-hz = /bits/ 64 <637000000>;
+ opp-microvolt = <712500>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-microvolt = <737500>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <756250>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-796000000 {
+ opp-hz = /bits/ 64 <796000000>;
+ opp-microvolt = <781250>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <800000>;
+ opp-supported-hw = <0x38>;
+ };
+
+ opp-900000000-3 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-900000000-4 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <837500>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-900000000-5 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <825000>;
+ opp-supported-hw = <0x30>;
+ };
+
+ opp-950000000-3 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <900000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-950000000-4 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <875000>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-950000000-5 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x30>;
+ };
+
+ opp-1000000000-3 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-1000000000-4 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <912500>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-1000000000-5 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <875000>;
+ opp-supported-hw = <0x30>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
@@ -813,7 +949,7 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
#size-cells = <0>;
#power-domain-cells = <1>;
- power-domain@MT8186_POWER_DOMAIN_MFG1 {
+ mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
reg = <MT8186_POWER_DOMAIN_MFG1>;
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
@@ -1606,6 +1742,8 @@ gpu: gpu@13040000 {
#cooling-cells = <2>;
nvmem-cells = <&gpu_speedbin>;
nvmem-cell-names = "speed-bin";
+ operating-points-v2 = <&gpu_opp_table>;
+ dynamic-power-coefficient = <4687>;
status = "disabled";
};
--
2.41.0.rc0.172.g3f132b7071-googIl 07/06/23 11:06, Chen-Yu Tsai ha scritto:
> Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
> adapted to the new upstream opp-supported-hw binning format. Also add
> dynamic-power-coefficient for the GPU.
>
> Also add label for mfg1 power domain. This is to be used at the board
> level to add a regulator supply for the power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++-
> 1 file changed, 139 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c58d7eb87b1d..a34489e27cd4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -695,6 +695,142 @@ clk32k: oscillator-32k {
> clock-output-names = "clk32k";
> };
>
> + gpu_opp_table: opp-table-gpu {
> + compatible = "operating-points-v2";
> +
> + opp-299000000 {
> + opp-hz = /bits/ 64 <299000000>;
> + opp-microvolt = <612500>;
> + opp-supported-hw = <0x38>;
For all of the OPPs that are supposed to be supported by all speed-bins, you don't
need to restrict them to all "known" bins.
Please change opp-supported-hw from <0x38> to <0xff>, which literally means
just "applies to all revisions".
> + };
..snip...
> +
> + opp-900000000-3 {
What about calling those like "opp-900000000-bin3"?
Makes it clear that it's tied to what MediaTek calls a speedbin "3" (as we're
interpreting the values in the nvmem driver to make them compatible with the
opp-supported-hw's expectations).
Cheers,
Angelo
On Thu, Jun 8, 2023 at 8:14 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 07/06/23 11:06, Chen-Yu Tsai ha scritto:
> > Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
> > adapted to the new upstream opp-supported-hw binning format. Also add
> > dynamic-power-coefficient for the GPU.
> >
> > Also add label for mfg1 power domain. This is to be used at the board
> > level to add a regulator supply for the power domain.
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++-
> > 1 file changed, 139 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > index c58d7eb87b1d..a34489e27cd4 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -695,6 +695,142 @@ clk32k: oscillator-32k {
> > clock-output-names = "clk32k";
> > };
> >
> > + gpu_opp_table: opp-table-gpu {
> > + compatible = "operating-points-v2";
> > +
> > + opp-299000000 {
> > + opp-hz = /bits/ 64 <299000000>;
> > + opp-microvolt = <612500>;
> > + opp-supported-hw = <0x38>;
>
> For all of the OPPs that are supposed to be supported by all speed-bins, you don't
> need to restrict them to all "known" bins.
>
> Please change opp-supported-hw from <0x38> to <0xff>, which literally means
> just "applies to all revisions".
OK.
> > + };
>
>
> ..snip...
>
> > +
> > + opp-900000000-3 {
>
> What about calling those like "opp-900000000-bin3"?
> Makes it clear that it's tied to what MediaTek calls a speedbin "3" (as we're
> interpreting the values in the nvmem driver to make them compatible with the
> opp-supported-hw's expectations).
I thought that at first as well, but the bindings require the OPP node to
be named following '^opp(-?[0-9]+)*$':, so numbers only.
ChenYu
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