Add memory-region property to the tegra186-bpmp binding to support
DRAM MRQ GSCs.

Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 .../firmware/nvidia,tegra186-bpmp.yaml        | 37 +++++++++++++++++--
 1 file changed, 34 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
index 833c07f1685c..f3e02c9d090d 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -57,8 +57,11 @@ description: |
   "#address-cells" or "#size-cells" property.
 
   The shared memory area for the IPC TX and RX between CPU and BPMP are
-  predefined and work on top of sysram, which is an SRAM inside the
-  chip. See ".../sram/sram.yaml" for the bindings.
+  predefined and work on top of either sysram, which is an SRAM inside the
+  chip, or in normal SDRAM.
+  See ".../sram/sram.yaml" for the bindings for the SRAM case.
+  See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
+  the SDRAM case.
 
 properties:
   compatible:
@@ -81,6 +84,11 @@ properties:
     minItems: 2
     maxItems: 2
 
+  memory-region:
+    description: phandle to reserved memory region used for IPC between
+      CPU-NS and BPMP.
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -115,10 +123,15 @@ properties:
 
 additionalProperties: false
 
+oneOf:
+  - required:
+      - memory-region
+  - required:
+      - shmem
+
 required:
   - compatible
   - mboxes
-  - shmem
   - "#clock-cells"
   - "#power-domain-cells"
   - "#reset-cells"
@@ -184,3 +197,21 @@ examples:
             #thermal-sensor-cells = <1>;
         };
     };
+
+  - |
+    #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+    bpmp {
+        compatible = "nvidia,tegra186-bpmp";
+        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+        interconnect-names = "read", "write", "dma-mem", "dma-write";
+        mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
+                            TEGRA_HSP_DB_MASTER_BPMP>;
+        memory-region = <&dram_cpu_bpmp_mail>;
+        #clock-cells = <1>;
+        #power-domain-cells = <1>;
+        #reset-cells = <1>;
+    };
-- 
2.34.1

On 10/05/2023 16:22, Peter De Schrijver wrote:
> Add memory-region property to the tegra186-bpmp binding to support
> DRAM MRQ GSCs.
> 
> Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---

Also no changelog. Since I do not see improvements after Thierry
comments I assume you send the same.

Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).

Best regards,
Krzysztof

On Wed, May 10, 2023 at 05:01:55PM +0200, Krzysztof Kozlowski wrote:
> On 10/05/2023 16:22, Peter De Schrijver wrote:
> > Add memory-region property to the tegra186-bpmp binding to support
> > DRAM MRQ GSCs.
> > 
> > Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> 
> Also no changelog. Since I do not see improvements after Thierry
> comments I assume you send the same.
> 

The changelog is in the cover letter. I will send it to you next
iteration.

Peter.

On 11/05/2023 10:04, Peter De Schrijver wrote:
> On Wed, May 10, 2023 at 05:01:55PM +0200, Krzysztof Kozlowski wrote:
>> On 10/05/2023 16:22, Peter De Schrijver wrote:
>>> Add memory-region property to the tegra186-bpmp binding to support
>>> DRAM MRQ GSCs.
>>>
>>> Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
>>> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>> ---
>>
>> Also no changelog. Since I do not see improvements after Thierry
>> comments I assume you send the same.
>>
> 
> The changelog is in the cover letter. I will send it to you next
> iteration.

I got only few patches, rest is missing including changelog. Thus it is
the same as it did not exist.


Best regards,
Krzysztof

On Thu, May 11, 2023 at 11:03:24AM +0200, Krzysztof Kozlowski wrote:
> On 11/05/2023 10:04, Peter De Schrijver wrote:
> > On Wed, May 10, 2023 at 05:01:55PM +0200, Krzysztof Kozlowski wrote:
> >> On 10/05/2023 16:22, Peter De Schrijver wrote:
> >>> Add memory-region property to the tegra186-bpmp binding to support
> >>> DRAM MRQ GSCs.
> >>>
> >>> Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> >>> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> >>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >>> ---
> >>
> >> Also no changelog. Since I do not see improvements after Thierry
> >> comments I assume you send the same.
> >>
> > 
> > The changelog is in the cover letter. I will send it to you next
> > iteration.
> 
> I got only few patches, rest is missing including changelog. Thus it is
> the same as it did not exist.
> 

Do you want all of them? Some people seem to object to that so I didn't
send them to all people.

Peter.

On 11/05/2023 12:31, Peter De Schrijver wrote:
> On Thu, May 11, 2023 at 11:03:24AM +0200, Krzysztof Kozlowski wrote:
>> On 11/05/2023 10:04, Peter De Schrijver wrote:
>>> On Wed, May 10, 2023 at 05:01:55PM +0200, Krzysztof Kozlowski wrote:
>>>> On 10/05/2023 16:22, Peter De Schrijver wrote:
>>>>> Add memory-region property to the tegra186-bpmp binding to support
>>>>> DRAM MRQ GSCs.
>>>>>
>>>>> Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
>>>>> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
>>>>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>> ---
>>>>
>>>> Also no changelog. Since I do not see improvements after Thierry
>>>> comments I assume you send the same.
>>>>
>>>
>>> The changelog is in the cover letter. I will send it to you next
>>> iteration.
>>
>> I got only few patches, rest is missing including changelog. Thus it is
>> the same as it did not exist.
>>
> 
> Do you want all of them? Some people seem to object to that so I didn't
> send them to all people.

If you do not send entire patchset to everyone, then cover letter should
reach everyone.

Best regards,
Krzysztof