The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
access from S-mode, but it doesn't need the edge quirk.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++
drivers/irqchip/irq-sifive-plic.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index f75736a061af..64b43a3c3748 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -62,6 +62,10 @@ properties:
- starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
+ - items:
+ - enum:
+ - thead,light-plic
+ - const: thead,c910-plic
- items:
- enum:
- allwinner,sun20i-d1-plic
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e1484905b7bd..71afa2a584d9 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node,
}
IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
+IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
static int __init plic_edge_init(struct device_node *node,
--
2.40.0
On 07/05/2023 20:23, Jisheng Zhang wrote: > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + Bindings are always separate patches. Please run scripts/checkpatch.pl and fix reported warnings. Best regards, Krzysztof
On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
> access from S-mode, but it doesn't need the edge quirk.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++
> drivers/irqchip/irq-sifive-plic.c | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index f75736a061af..64b43a3c3748 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -62,6 +62,10 @@ properties:
> - starfive,jh7110-plic
> - canaan,k210-plic
> - const: sifive,plic-1.0.0
> + - items:
> + - enum:
> + - thead,light-plic
> + - const: thead,c910-plic
> - items:
> - enum:
> - allwinner,sun20i-d1-plic
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index e1484905b7bd..71afa2a584d9 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node,
> }
>
> IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init);
> IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
>
> static int __init plic_edge_init(struct device_node *node,
> --
> 2.40.0
>
opensbi needs thead,c900-plic, and we could put multi compatible name
in the dts. So, it's no need here.
Another question, Could we change the name of Sifive to RISC-V when
"cat /proc/interrupts" ?
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index ff47bd0dec45..b5844d784bfa 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -177,7 +177,7 @@ static int plic_set_affinity(struct irq_data *d,
#endif
static struct irq_chip plic_edge_chip = {
- .name = "SiFive PLIC",
+ .name = "RISC-V PLIC",
.irq_enable = plic_irq_enable,
.irq_disable = plic_irq_disable,
.irq_ack = plic_irq_eoi,
@@ -192,7 +192,7 @@ static struct irq_chip plic_edge_chip = {
};
static struct irq_chip plic_chip = {
- .name = "SiFive PLIC",
+ .name = "RISC-V PLIC",
.irq_enable = plic_irq_enable,
.irq_disable = plic_irq_disable,
.irq_mask = plic_irq_mask,
--
Best Regards
Guo Ren
On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote: > On Mon, May 8, 2023 at 2:34 AM Jisheng Zhang <jszhang@kernel.org> wrote: > > > > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > > access from S-mode, but it doesn't need the edge quirk. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > > drivers/irqchip/irq-sifive-plic.c | 1 + > > 2 files changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > index f75736a061af..64b43a3c3748 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -62,6 +62,10 @@ properties: > > - starfive,jh7110-plic > > - canaan,k210-plic > > - const: sifive,plic-1.0.0 > > + - items: > > + - enum: > > + - thead,light-plic > > + - const: thead,c910-plic > > - items: > > - enum: > > - allwinner,sun20i-d1-plic > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index e1484905b7bd..71afa2a584d9 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > > } > > > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > > > static int __init plic_edge_init(struct device_node *node, > > -- > > 2.40.0 > > > opensbi needs thead,c900-plic, and we could put multi compatible name > in the dts. So, it's no need here. Thanks, I misunderstood the PLIC edge quirk. This patch isn't needed any more.
On Mon, May 08, 2023 at 02:52:29PM +0800, Guo Ren wrote: > Another question, Could we change the name of Sifive to RISC-V when > "cat /proc/interrupts" ? Previously NAKed by Marc as it is ABI: https://lore.kernel.org/all/20511a05f39408c8ffbcc98923c4abd2@kernel.org Cheers, Conor.
在 2023-05-08星期一的 02:23 +0800,Jisheng Zhang写道:
> The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
> access from S-mode, but it doesn't need the edge quirk.
No, the PLIC controller seems to be the same between C906 and C910,
which has level/edge selectable via external signal.
See openc906 and openc910 repositories, especially the documents with
it: 玄铁C9{06,10}集成手册.pdf .
In addition, such problem won't arise when the system uses only level-
triggered interrupts.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4
> ++++
> drivers/irqchip/irq-sifive-plic.c | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-
> 1.0.0.yaml
> index f75736a061af..64b43a3c3748 100644
> --- a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> @@ -62,6 +62,10 @@ properties:
> - starfive,jh7110-plic
> - canaan,k210-plic
> - const: sifive,plic-1.0.0
> + - items:
> + - enum:
> + - thead,light-plic
> + - const: thead,c910-plic
> - items:
> - enum:
> - allwinner,sun20i-d1-plic
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-
> sifive-plic.c
> index e1484905b7bd..71afa2a584d9 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node
> *node,
> }
>
> IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init);
> IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for
> legacy systems */
>
> static int __init plic_edge_init(struct device_node *node,
Hey Jisheng, On Mon, May 08, 2023 at 02:23:00AM +0800, Jisheng Zhang wrote: > The T-HEAD's C910 PLIC still needs the delegation bit settingto allow > access from S-mode, but it doesn't need the edge quirk. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ > drivers/irqchip/irq-sifive-plic.c | 1 + dt-bindings changes need to be in their own patch. > 2 files changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index f75736a061af..64b43a3c3748 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -62,6 +62,10 @@ properties: > - starfive,jh7110-plic > - canaan,k210-plic > - const: sifive,plic-1.0.0 > + - items: > + - enum: > + - thead,light-plic If "light" is a code name, but "TH1520" is what this is known as to the wider world, I think we should use thead,th1520-plic here. Thanks, Conor. > + - const: thead,c910-plic > - items: > - enum: > - allwinner,sun20i-d1-plic > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index e1484905b7bd..71afa2a584d9 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, > } > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > > static int __init plic_edge_init(struct device_node *node, > -- > 2.40.0 >
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