TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
however MIPI DSI output only seems to work when PLL_MIPI is selected and
thus the choice must be hardcoded in.
Currently, this driver can't propagate rate change from N-K-M clocks
(such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
in setting of the TCON0 data clock rate, limiting the precision with
which a target pixel clock can be matched.
For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
can deviate up to 8% off target.
Signed-off-by: Roman Beranek <me@crly.cz>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 41519185600a..eb36f8f77d55 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
+/*
+ * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
+ * the mux from reparenting.
+ */
+#define SUN50I_A64_TCON0_CLK_REG 0x118
+
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
tcon0_table, 0x118, 24, 3, BIT(31),
- CLK_SET_RATE_PARENT);
+ CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT);
static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
static const u8 tcon1_table[] = { 0, 2, };
@@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ /* Set PLL MIPI as parent for TCON0 */
+ val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+ val &= ~GENMASK(26, 24);
+ writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
+
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
if (ret)
return ret;
--
2.32.0 (Apple Git-132)On Thu, May 4, 2023 at 10:34 PM Roman Beranek <me@crly.cz> wrote:
>
> TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> however MIPI DSI output only seems to work when PLL_MIPI is selected and
> thus the choice must be hardcoded in.
>
> Currently, this driver can't propagate rate change from N-K-M clocks
> (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
> in setting of the TCON0 data clock rate, limiting the precision with
> which a target pixel clock can be matched.
>
> For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
> can deviate up to 8% off target.
Hi Roman,
I'm a bit late, but this patch breaks the LCD on Pine64 Pinebook. When
TCON0 parent is pll-mipi, the panel is blank and I get vblank timeouts.
With this patch reverted it works if I force pll-video-2x as a parent for TCON0.
So for me RGB output doesn't seem to work with PLL_MIPI, but works
only with PLL_VIDEO0_2X. Any ideas on how to fix it?
Regards,
Vasily
> Signed-off-by: Roman Beranek <me@crly.cz>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index 41519185600a..eb36f8f77d55 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
> 0x104, 0, 4, 24, 3, BIT(31),
> CLK_SET_RATE_PARENT);
>
> +/*
> + * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
> + * the mux from reparenting.
> + */
> +#define SUN50I_A64_TCON0_CLK_REG 0x118
> +
> static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
> static const u8 tcon0_table[] = { 0, 2, };
> static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
> tcon0_table, 0x118, 24, 3, BIT(31),
> - CLK_SET_RATE_PARENT);
> + CLK_SET_RATE_PARENT |
> + CLK_SET_RATE_NO_REPARENT);
>
> static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> static const u8 tcon1_table[] = { 0, 2, };
> @@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>
> writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
>
> + /* Set PLL MIPI as parent for TCON0 */
> + val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
> + val &= ~GENMASK(26, 24);
> + writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
> +
> ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
> if (ret)
> return ret;
> --
> 2.32.0 (Apple Git-132)
>
>
On Fri, Dec 13, 2024 at 10:29 PM Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>
> On Thu, May 4, 2023 at 10:34 PM Roman Beranek <me@crly.cz> wrote:
> >
> > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> > however MIPI DSI output only seems to work when PLL_MIPI is selected and
> > thus the choice must be hardcoded in.
> >
> > Currently, this driver can't propagate rate change from N-K-M clocks
> > (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
> > in setting of the TCON0 data clock rate, limiting the precision with
> > which a target pixel clock can be matched.
> >
> > For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
> > can deviate up to 8% off target.
>
> Hi Roman,
>
> I'm a bit late, but this patch breaks the LCD on Pine64 Pinebook. When
> TCON0 parent is pll-mipi, the panel is blank and I get vblank timeouts.
>
> With this patch reverted it works if I force pll-video-2x as a parent for TCON0.
And changing TCON0 parent in runtime by poking CCU registers also
fixes the issue (even though pll-video-2x is *much* slower than
pll-mipi), i.e. if I do "devmem2 0x01c20118 w 0x82000000" the picture
appears on the screen.
> So for me RGB output doesn't seem to work with PLL_MIPI, but works
> only with PLL_VIDEO0_2X. Any ideas on how to fix it?
>
> Regards,
> Vasily
>
>
>
> > Signed-off-by: Roman Beranek <me@crly.cz>
> > ---
> > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > index 41519185600a..eb36f8f77d55 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > @@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
> > 0x104, 0, 4, 24, 3, BIT(31),
> > CLK_SET_RATE_PARENT);
> >
> > +/*
> > + * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
> > + * the mux from reparenting.
> > + */
> > +#define SUN50I_A64_TCON0_CLK_REG 0x118
> > +
> > static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
> > static const u8 tcon0_table[] = { 0, 2, };
> > static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
> > tcon0_table, 0x118, 24, 3, BIT(31),
> > - CLK_SET_RATE_PARENT);
> > + CLK_SET_RATE_PARENT |
> > + CLK_SET_RATE_NO_REPARENT);
> >
> > static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> > static const u8 tcon1_table[] = { 0, 2, };
> > @@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> >
> > writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
> >
> > + /* Set PLL MIPI as parent for TCON0 */
> > + val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
> > + val &= ~GENMASK(26, 24);
> > + writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
> > +
> > ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
> > if (ret)
> > return ret;
> > --
> > 2.32.0 (Apple Git-132)
> >
> >
Dne petek, 05. maj 2023 ob 07:21:07 CEST je Roman Beranek napisal(a): > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), > however MIPI DSI output only seems to work when PLL_MIPI is selected and > thus the choice must be hardcoded in. > > Currently, this driver can't propagate rate change from N-K-M clocks > (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating > in setting of the TCON0 data clock rate, limiting the precision with > which a target pixel clock can be matched. > > For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock > can deviate up to 8% off target. > > Signed-off-by: Roman Beranek <me@crly.cz> Applied, thanks! Best regards, Jernej
Dne petek, 05. maj 2023 ob 07:21:07 CEST je Roman Beranek napisal(a): > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), > however MIPI DSI output only seems to work when PLL_MIPI is selected and > thus the choice must be hardcoded in. > > Currently, this driver can't propagate rate change from N-K-M clocks > (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating > in setting of the TCON0 data clock rate, limiting the precision with > which a target pixel clock can be matched. > > For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock > can deviate up to 8% off target. > > Signed-off-by: Roman Beranek <me@crly.cz> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
On Fri, May 05, 2023 at 07:21:07AM +0200, Roman Beranek wrote: > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), > however MIPI DSI output only seems to work when PLL_MIPI is selected and > thus the choice must be hardcoded in. > > Currently, this driver can't propagate rate change from N-K-M clocks > (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating > in setting of the TCON0 data clock rate, limiting the precision with > which a target pixel clock can be matched. > > For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock > can deviate up to 8% off target. > > Signed-off-by: Roman Beranek <me@crly.cz> Acked-by: Maxime Ripard <maxime@cerno.tech>
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