From: Alexander Bahle <bahle@ibv-augsburg.de>
Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for
setting the PCIe PHY latencies.
The properties expect a list of uint32 PHY latencies in picoseconds for
every supported speed starting at PCIe Gen1, e.g.:
tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */
rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */
Signed-off-by: Alexander Bahle <bahle@ibv-augsburg.de>
Signed-off-by: Dominic Rath <rath@ibv-augsburg.de>
---
.../bindings/phy/phy-cadence-torrent.yaml | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 2ad1faadda2a..93228a304395 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -126,6 +126,24 @@ patternProperties:
enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
default: 8100
+ tx-phy-latency-ps:
+ description:
+ The PHY latencies for the TX direction applied to PCIe PTM timestamps. Most
+ PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+ accurate PTM timestamps, the PCIe PTM specification requires that the time
+ at which the first serial bit is present on the serial lines be taken.
+ Should contain picosecond latency values for each supported speed,
+ starting with Gen1 latency.
+
+ rx-phy-latency-ps:
+ description:
+ The PHY latencies for the RX direction applied to the PTM timestamps. Most
+ PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
+ accurate PTM timestamps, the PCIe PTM specification requires that the time
+ at which the first serial bit is present on the serial lines be taken.
+ Should contain picosecond latency values for each supported speed,
+ starting with Gen1 latency.
+
required:
- reg
- resets
@@ -203,6 +221,8 @@ examples:
cdns,phy-type = <PHY_TYPE_PCIE>;
cdns,num-lanes = <2>;
cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
+ tx-phy-latency-ps = <138800 69400>;
+ rx-phy-latency-ps = <185200 92600>;
};
phy@2 {
--
2.36.0>
> From: Alexander Bahle <bahle@ibv-augsburg.de>
>
> Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for
> setting the PCIe PHY latencies.
> The properties expect a list of uint32 PHY latencies in picoseconds for
> every supported speed starting at PCIe Gen1, e.g.:
>
> tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */
> rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */
>
> Signed-off-by: Alexander Bahle <bahle@ibv-augsburg.de>
> Signed-off-by: Dominic Rath <rath@ibv-augsburg.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
> .../bindings/phy/phy-cadence-torrent.yaml | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 2ad1faadda2a..93228a304395 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -126,6 +126,24 @@ patternProperties:
> enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
> default: 8100
>
> + tx-phy-latency-ps:
> + description:
> + The PHY latencies for the TX direction applied to PCIe PTM timestamps. Most
> + PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
> + accurate PTM timestamps, the PCIe PTM specification requires that the time
> + at which the first serial bit is present on the serial lines be taken.
> + Should contain picosecond latency values for each supported speed,
> + starting with Gen1 latency.
> +
> + rx-phy-latency-ps:
> + description:
> + The PHY latencies for the RX direction applied to the PTM timestamps. Most
> + PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
> + accurate PTM timestamps, the PCIe PTM specification requires that the time
> + at which the first serial bit is present on the serial lines be taken.
> + Should contain picosecond latency values for each supported speed,
> + starting with Gen1 latency.
> +
> required:
> - reg
> - resets
> @@ -203,6 +221,8 @@ examples:
> cdns,phy-type = <PHY_TYPE_PCIE>;
> cdns,num-lanes = <2>;
> cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
> + tx-phy-latency-ps = <138800 69400>;
> + rx-phy-latency-ps = <185200 92600>;
> };
>
> phy@2 {
> --
> 2.36.0
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: > From: Alexander Bahle <bahle@ibv-augsburg.de> > > Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > setting the PCIe PHY latencies. > The properties expect a list of uint32 PHY latencies in picoseconds for > every supported speed starting at PCIe Gen1, e.g.: > > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ Are these things that could/should be described in a more generic place? They don't look necessarily Cadence-specific. Bjorn
Hi Bjorn, > > On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: > > From: Alexander Bahle <bahle@ibv-augsburg.de> > > > > Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > > setting the PCIe PHY latencies. > > The properties expect a list of uint32 PHY latencies in picoseconds for > > every supported speed starting at PCIe Gen1, e.g.: > > > > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ > > Are these things that could/should be described in a more generic > place? They don't look necessarily Cadence-specific. > As there is currently no generic binding, would you like to see a new yaml binding added (Documentation/devicetree/bindings/phy/phy.yaml) that contains just the two phy properties? -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy
On Tue, May 09, 2023 at 05:31:19PM +0200, Christian Gmeiner wrote: > > On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: > > > From: Alexander Bahle <bahle@ibv-augsburg.de> > > > > > > Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > > > setting the PCIe PHY latencies. > > > The properties expect a list of uint32 PHY latencies in picoseconds for > > > every supported speed starting at PCIe Gen1, e.g.: > > > > > > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > > > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ > > > > Are these things that could/should be described in a more generic > > place? They don't look necessarily Cadence-specific. > > As there is currently no generic binding, would you like to see a new > yaml binding > added (Documentation/devicetree/bindings/phy/phy.yaml) that contains just the > two phy properties? The whole thing is more a question for Rob. Bjorn
On 09/05/2023 23:57, Bjorn Helgaas wrote: > On Tue, May 09, 2023 at 05:31:19PM +0200, Christian Gmeiner wrote: >>> On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: >>>> From: Alexander Bahle <bahle@ibv-augsburg.de> >>>> >>>> Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for >>>> setting the PCIe PHY latencies. >>>> The properties expect a list of uint32 PHY latencies in picoseconds for >>>> every supported speed starting at PCIe Gen1, e.g.: >>>> >>>> tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ >>>> rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ >>> >>> Are these things that could/should be described in a more generic >>> place? They don't look necessarily Cadence-specific. >> >> As there is currently no generic binding, would you like to see a new >> yaml binding >> added (Documentation/devicetree/bindings/phy/phy.yaml) that contains just the >> two phy properties? > > The whole thing is more a question for Rob. For which you might wait a bit currently. If the question is only about location of the properties - device schema or something generic - then for now you can keep it here. Moving to generic schema is always easy later. Better to have proper names for properties. Best regards, Krzysztof
On Wed, May 10, 2023 at 09:08:39AM +0200, Krzysztof Kozlowski wrote: > On 09/05/2023 23:57, Bjorn Helgaas wrote: > > On Tue, May 09, 2023 at 05:31:19PM +0200, Christian Gmeiner wrote: > >>> On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: > >>>> From: Alexander Bahle <bahle@ibv-augsburg.de> > >>>> > >>>> Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > >>>> setting the PCIe PHY latencies. > >>>> The properties expect a list of uint32 PHY latencies in picoseconds for > >>>> every supported speed starting at PCIe Gen1, e.g.: > >>>> > >>>> tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > >>>> rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ > >>> > >>> Are these things that could/should be described in a more generic > >>> place? They don't look necessarily Cadence-specific. > >> > >> As there is currently no generic binding, would you like to see a new > >> yaml binding > >> added (Documentation/devicetree/bindings/phy/phy.yaml) that contains just the > >> two phy properties? > > > > The whole thing is more a question for Rob. > > For which you might wait a bit currently. > > If the question is only about location of the properties - device schema > or something generic - then for now you can keep it here. Moving to > generic schema is always easy later. > > Better to have proper names for properties. Good point. The current names seem fine to me since the names themselves aren't Cadence-specific. Bjorn
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