On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
to enable enumerating this chip.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index adbda4dccdd5..eca5df85fe33 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -565,6 +565,13 @@ flash@0 {
};
};
+&pcie1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins_default>;
+};
+
&pio {
mediatek,rsel-resistance-in-si-unit;
pinctrl-names = "default";
@@ -959,6 +966,24 @@ pins-vreg-en {
};
};
+ pcie0_pins_default: pcie0-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
+ <PINMUX_GPIO20__FUNC_PERSTN>,
+ <PINMUX_GPIO21__FUNC_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_pins_default: pcie1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
+ <PINMUX_GPIO23__FUNC_CLKREQN_1>,
+ <PINMUX_GPIO24__FUNC_WAKEN_1>;
+ bias-pull-up;
+ };
+ };
+
pio_default: pio-default-pins {
pins-wifi-enable {
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
--
2.40.0
On 24/04/2023 13:25, AngeloGioacchino Del Regno wrote:
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Applied, thanks
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index adbda4dccdd5..eca5df85fe33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -565,6 +565,13 @@ flash@0 {
> };
> };
>
> +&pcie1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins_default>;
> +};
> +
> &pio {
> mediatek,rsel-resistance-in-si-unit;
> pinctrl-names = "default";
> @@ -959,6 +966,24 @@ pins-vreg-en {
> };
> };
>
> + pcie0_pins_default: pcie0-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
> + <PINMUX_GPIO20__FUNC_PERSTN>,
> + <PINMUX_GPIO21__FUNC_CLKREQN>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_pins_default: pcie1-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
> + <PINMUX_GPIO23__FUNC_CLKREQN_1>,
> + <PINMUX_GPIO24__FUNC_WAKEN_1>;
> + bias-pull-up;
> + };
> + };
> +
> pio_default: pio-default-pins {
> pins-wifi-enable {
> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
On 24/04/2023 13:25, AngeloGioacchino Del Regno wrote: > On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected > over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports > to enable enumerating this chip. > > Signed-off-by: AngeloGioacchino Del Regno<angelogioacchino.delregno@collabora.com> > Tested-by: Chen-Yu Tsai<wenst@chromium.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Regards, Alexandre
On Mon, Apr 24, 2023 at 7:25 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index adbda4dccdd5..eca5df85fe33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -565,6 +565,13 @@ flash@0 {
> };
> };
>
> +&pcie1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins_default>;
> +};
> +
> &pio {
> mediatek,rsel-resistance-in-si-unit;
> pinctrl-names = "default";
> @@ -959,6 +966,24 @@ pins-vreg-en {
> };
> };
>
> + pcie0_pins_default: pcie0-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
> + <PINMUX_GPIO20__FUNC_PERSTN>,
> + <PINMUX_GPIO21__FUNC_CLKREQN>;
> + bias-pull-up;
> + };
> + };
I think we should remove this. We can add it later with the actual device
that has NVMe.
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> + pcie1_pins_default: pcie1-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
> + <PINMUX_GPIO23__FUNC_CLKREQN_1>,
> + <PINMUX_GPIO24__FUNC_WAKEN_1>;
> + bias-pull-up;
> + };
> + };
> +
> pio_default: pio-default-pins {
> pins-wifi-enable {
> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
> --
> 2.40.0
>
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