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[PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node

Bartosz Golaszewski posted 7 patches 2 years, 10 months ago
There is a newer version of this series
[PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Posted by Bartosz Golaszewski 2 years, 10 months ago 
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

Add the Adreno GPU IOMMU for sa8775p-based platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 191b510b5a1a..11f3d80dd869 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
+				     "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_HUB_AON_CLK>;
+			clock-names = "gcc_gpu_memnoc_gfx_clk",
+				      "gcc_gpu_snoc_dvm_gfx_clk",
+				      "gpu_cc_ahb_clk",
+				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
+				      "gpu_cc_cx_gmu_clk",
+				      "gpu_cc_hub_cx_int_clk",
+				      "gpu_cc_hub_aon_clk";
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,
-- 
2.37.2
Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Posted by Konrad Dybcio 2 years, 10 months ago 

On 11.04.2023 14:59, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Add the Adreno GPU IOMMU for sa8775p-based platforms.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 191b510b5a1a..11f3d80dd869 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
>  #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3da0000 {
> +			compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
> +				     "arm,mmu-500";
Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible
which means it's getting bound to the generic SMMU driver (without
QC quirks). If that was a mistake, you should have had all 4

"qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500"

Without falling into the qc-specific codepaths, the Adreno compat does
nothing.

Konrad
> +			reg = <0x0 0x03da0000 0x0 0x20000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <2>;
> +			dma-coherent;
> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> +				 <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> +				 <&gpucc GPU_CC_HUB_AON_CLK>;
> +			clock-names = "gcc_gpu_memnoc_gfx_clk",
> +				      "gcc_gpu_snoc_dvm_gfx_clk",
> +				      "gpu_cc_ahb_clk",
> +				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
> +				      "gpu_cc_cx_gmu_clk",
> +				      "gpu_cc_hub_cx_int_clk",
> +				      "gpu_cc_hub_aon_clk";
> +			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
>  			reg = <0x0 0x0b220000 0x0 0x30000>,
Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Posted by Bartosz Golaszewski 2 years, 10 months ago 
On Tue, Apr 11, 2023 at 3:16 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 11.04.2023 14:59, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >
> > Add the Adreno GPU IOMMU for sa8775p-based platforms.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > index 191b510b5a1a..11f3d80dd869 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > @@ -7,6 +7,7 @@
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/clock/qcom,rpmh.h>
> >  #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> > +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
> >  #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> >  #include <dt-bindings/power/qcom-rpmpd.h>
> >  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 {
> >                       #power-domain-cells = <1>;
> >               };
> >
> > +             adreno_smmu: iommu@3da0000 {
> > +                     compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
> > +                                  "arm,mmu-500";
> Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible
> which means it's getting bound to the generic SMMU driver (without
> QC quirks). If that was a mistake, you should have had all 4
>
> "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500"
>
> Without falling into the qc-specific codepaths, the Adreno compat does
> nothing.
>

I did that initially, then noticed dtbs_check fails because the
existing adreno GPUs implementing "arm,smmu-500" expect three
compatibles like in this commit. I did that and the driver still
probed the same so I assumed all's good. You're right of course, the
adreno impl is not being assigned without "qcom,smmu-500". Are the
bindings wrong in this case and should it be something like the
following?

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d966dc65ce10..cd1b052a7242 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -84,6 +84,7 @@ properties:
               - qcom,sm8150-smmu-500
               - qcom,sm8250-smmu-500
           - const: qcom,adreno-smmu
+          - const: qcom,smmu-500
           - const: arm,mmu-500
       - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
         items:

Bartosz

> Konrad
> > +                     reg = <0x0 0x03da0000 0x0 0x20000>;
> > +                     #iommu-cells = <2>;
> > +                     #global-interrupts = <2>;
> > +                     dma-coherent;
> > +                     power-domains = <&gpucc GPU_CC_CX_GDSC>;
> > +                     clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> > +                              <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> > +                              <&gpucc GPU_CC_AHB_CLK>,
> > +                              <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> > +                              <&gpucc GPU_CC_CX_GMU_CLK>,
> > +                              <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> > +                              <&gpucc GPU_CC_HUB_AON_CLK>;
> > +                     clock-names = "gcc_gpu_memnoc_gfx_clk",
> > +                                   "gcc_gpu_snoc_dvm_gfx_clk",
> > +                                   "gpu_cc_ahb_clk",
> > +                                   "gpu_cc_hlos1_vote_gpu_smmu_clk",
> > +                                   "gpu_cc_cx_gmu_clk",
> > +                                   "gpu_cc_hub_cx_int_clk",
> > +                                   "gpu_cc_hub_aon_clk";
> > +                     interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> > +             };
> > +
> >               pdc: interrupt-controller@b220000 {
> >                       compatible = "qcom,sa8775p-pdc", "qcom,pdc";
> >                       reg = <0x0 0x0b220000 0x0 0x30000>,
Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Posted by Konrad Dybcio 2 years, 10 months ago 

On 11.04.2023 16:41, Bartosz Golaszewski wrote:
> On Tue, Apr 11, 2023 at 3:16 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 11.04.2023 14:59, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>>
>>> Add the Adreno GPU IOMMU for sa8775p-based platforms.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++
>>>  1 file changed, 37 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> index 191b510b5a1a..11f3d80dd869 100644
>>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>>> @@ -7,6 +7,7 @@
>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>  #include <dt-bindings/clock/qcom,rpmh.h>
>>>  #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
>>> +#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
>>>  #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
>>>  #include <dt-bindings/power/qcom-rpmpd.h>
>>>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>> @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 {
>>>                       #power-domain-cells = <1>;
>>>               };
>>>
>>> +             adreno_smmu: iommu@3da0000 {
>>> +                     compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
>>> +                                  "arm,mmu-500";
>> Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible
>> which means it's getting bound to the generic SMMU driver (without
>> QC quirks). If that was a mistake, you should have had all 4
>>
>> "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500"
>>
>> Without falling into the qc-specific codepaths, the Adreno compat does
>> nothing.
>>
> 
> I did that initially, then noticed dtbs_check fails because the
> existing adreno GPUs implementing "arm,smmu-500" expect three
> compatibles like in this commit. I did that and the driver still
> probed the same so I assumed all's good. You're right of course, the
> adreno impl is not being assigned without "qcom,smmu-500". Are the
> bindings wrong in this case and should it be something like the
> following?
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index d966dc65ce10..cd1b052a7242 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -84,6 +84,7 @@ properties:
>                - qcom,sm8150-smmu-500
>                - qcom,sm8250-smmu-500
>            - const: qcom,adreno-smmu
> +          - const: qcom,smmu-500
>            - const: arm,mmu-500
>        - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
>          items:
> 
> Bartosz
Check

https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/commit/?h=for-joerg/arm-smmu/bindings&id=5c3686616b1840b3143b227eb58fb1c1621d204e

Konrad
> 
>> Konrad
>>> +                     reg = <0x0 0x03da0000 0x0 0x20000>;
>>> +                     #iommu-cells = <2>;
>>> +                     #global-interrupts = <2>;
>>> +                     dma-coherent;
>>> +                     power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>> +                     clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> +                              <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>> +                              <&gpucc GPU_CC_AHB_CLK>,
>>> +                              <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>> +                              <&gpucc GPU_CC_CX_GMU_CLK>,
>>> +                              <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>> +                              <&gpucc GPU_CC_HUB_AON_CLK>;
>>> +                     clock-names = "gcc_gpu_memnoc_gfx_clk",
>>> +                                   "gcc_gpu_snoc_dvm_gfx_clk",
>>> +                                   "gpu_cc_ahb_clk",
>>> +                                   "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>> +                                   "gpu_cc_cx_gmu_clk",
>>> +                                   "gpu_cc_hub_cx_int_clk",
>>> +                                   "gpu_cc_hub_aon_clk";
>>> +                     interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                  <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
>>> +             };
>>> +
>>>               pdc: interrupt-controller@b220000 {
>>>                       compatible = "qcom,sa8775p-pdc", "qcom,pdc";
>>>                       reg = <0x0 0x0b220000 0x0 0x30000>,

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