1. Patchew
  2. linux
  3. [PATCH v14 0/8] arm64: j721s2: Add support for additional IPs
  4. View patch

[PATCH v14 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support

Ravi Gunasekaran posted 8 patches 2 years, 10 months ago
[PATCH v14 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
Posted by Ravi Gunasekaran 2 years, 10 months ago 
From: Aswath Govindraju <a-govindraju@ti.com>

The board uses lane 1 of SERDES for USB. Set the mux
accordingly.

The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
I had reviewed this patch in the v5 series [0].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.

[0] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@ti.com/

Changes from v13:
* No changes. Only rebased on top of linux-next

Changes from v12:
* No change

Changes from v11:
* No change

Changes from v10:
* Removed Link tag from commit message

Changes from v9:
* Enabled USB nodes

Changes from v8:
* No change

Changes from v7:
* No change

Changes from v6:
* No change

Changes from v5:
* Removed Cc tags from commit message

Changes from v4:
* No change

Changes from v3:
* No change

Changes from v2:
* No change

Changes from v1:
* No change

 .../dts/ti/k3-j721s2-common-proc-board.dts    | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 1afefaf3f974..5c4ffb8124ca 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@
 			J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
 		>;
 	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
 };
 
 &wkup_pmx0 {
@@ -345,6 +351,23 @@
 	};
 };
 
+&usb_serdes_mux {
+	idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+	status = "okay";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
+
 &mcu_mcan0 {
 	status = "okay";
 	pinctrl-names = "default";
-- 
2.17.1
Re: [PATCH v14 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
Posted by Roger Quadros 2 years, 9 months ago 

On 31/03/2023 12:00, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <a-govindraju@ti.com>
> 
> The board uses lane 1 of SERDES for USB. Set the mux
> accordingly.
> 
> The USB controller and EVM supports super-speed for USB0
> on the Type-C port. However, the SERDES has a limitation
> that up to 2 protocols can be used at a time. The SERDES is
> wired for PCIe, eDP and USB super-speed. It has been
> chosen to use PCIe and eDP as default. So restrict
> USB0 to high-speed mode.
> 
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
> I had reviewed this patch in the v5 series [0].
> Since I'm taking over upstreaming this series, I removed the self
> Reviewed-by tag.
> 
> [0] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@ti.com/
> 
> Changes from v13:
> * No changes. Only rebased on top of linux-next
> 
> Changes from v12:
> * No change
> 
> Changes from v11:
> * No change
> 
> Changes from v10:
> * Removed Link tag from commit message
> 
> Changes from v9:
> * Enabled USB nodes
> 
> Changes from v8:
> * No change
> 
> Changes from v7:
> * No change
> 
> Changes from v6:
> * No change
> 
> Changes from v5:
> * Removed Cc tags from commit message
> 
> Changes from v4:
> * No change
> 
> Changes from v3:
> * No change
> 
> Changes from v2:
> * No change
> 
> Changes from v1:
> * No change
> 
>  .../dts/ti/k3-j721s2-common-proc-board.dts    | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index 1afefaf3f974..5c4ffb8124ca 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -147,6 +147,12 @@
>  			J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>  		>;
>  	};
> +
> +	main_usbss0_pins_default: main-usbss0-pins-default {
> +		pinctrl-single,pins = <
> +			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */

What about USB0_ID pin?

> +		>;
> +	};
>  };
>  
>  &wkup_pmx0 {
> @@ -345,6 +351,23 @@
>  	};
>  };
>  
> +&usb_serdes_mux {
> +	idle-states = <1>; /* USB0 to SERDES lane 1 */
> +};
> +
> +&usbss0 {
> +	status = "okay";
> +	pinctrl-0 = <&main_usbss0_pins_default>;
> +	pinctrl-names = "default";
> +	ti,vbus-divider;
> +	ti,usb2-only;
> +};
> +
> +&usb0 {
> +	dr_mode = "otg";
> +	maximum-speed = "high-speed";

Why is super-speed not possible?
I understood that SERDES lane 1 can be used for USB super-speed.

> +};
> +
>  &mcu_mcan0 {
>  	status = "okay";
>  	pinctrl-names = "default";

cheers,
-roger
Re: [PATCH v14 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
Posted by Ravi Gunasekaran 2 years, 9 months ago 

On 25/04/23 5:31 pm, Roger Quadros wrote:
> 
> 
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <a-govindraju@ti.com>
>>
>> The board uses lane 1 of SERDES for USB. Set the mux
>> accordingly.
>>
>> The USB controller and EVM supports super-speed for USB0
>> on the Type-C port. However, the SERDES has a limitation
>> that up to 2 protocols can be used at a time. The SERDES is
>> wired for PCIe, eDP and USB super-speed. It has been
>> chosen to use PCIe and eDP as default. So restrict
>> USB0 to high-speed mode.
>>
>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
>> ---
>> I had reviewed this patch in the v5 series [0].
>> Since I'm taking over upstreaming this series, I removed the self
>> Reviewed-by tag.
>>

[...]

>> * No change
>>
>>  .../dts/ti/k3-j721s2-common-proc-board.dts    | 23 +++++++++++++++++++
>>  1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> index 1afefaf3f974..5c4ffb8124ca 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> @@ -147,6 +147,12 @@
>>  			J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>>  		>;
>>  	};
>> +
>> +	main_usbss0_pins_default: main-usbss0-pins-default {
>> +		pinctrl-single,pins = <
>> +			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
> 
> What about USB0_ID pin?
> 

The pin (AC9) for USB0_ID signal is not multiplexed with any other signals.
Please see Page 51 in [0].

>> +		>;
>> +	};
>>  };
>>  

[...]

>> +
>> +&usb0 {
>> +	dr_mode = "otg";
>> +	maximum-speed = "high-speed";
> 
> Why is super-speed not possible?
> I understood that SERDES lane 1 can be used for USB super-speed.

The SerDes on J721S2 can simultaneously support only two protocols.
By default PCIe and DP will be supported. Due to this, USB is configured
in high-speed and this does not require any SerDes lane configuration.

> 
>> +};
>> +
>>  &mcu_mcan0 {
>>  	status = "okay";
>>  	pinctrl-names = "default";
> 
> cheers,
> -roger

[0] https://www.ti.com/lit/gpn/TDA4AL-Q1 

-- 
Regards,
Ravi

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.