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[PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz

Bartosz Wawrzyniak posted 1 patch 3 years ago 
drivers/net/ethernet/cadence/macb.h      | 2 ++
drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
2 files changed, 7 insertions(+), 1 deletion(-)
[PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Bartosz Wawrzyniak 3 years ago 
Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
---
 drivers/net/ethernet/cadence/macb.h      | 2 ++
 drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 14dfec4db8f9..c1fc91c97cee 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -692,6 +692,8 @@
 #define GEM_CLK_DIV48				3
 #define GEM_CLK_DIV64				4
 #define GEM_CLK_DIV96				5
+#define GEM_CLK_DIV128				6
+#define GEM_CLK_DIV224				7
 
 /* Constants for MAN register */
 #define MACB_MAN_C22_SOF			1
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 6e141a8bbf43..8708af6d25ed 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -2641,8 +2641,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
 		config = GEM_BF(CLK, GEM_CLK_DIV48);
 	else if (pclk_hz <= 160000000)
 		config = GEM_BF(CLK, GEM_CLK_DIV64);
-	else
+	else if (pclk_hz <= 240000000)
 		config = GEM_BF(CLK, GEM_CLK_DIV96);
+	else if (pclk_hz <= 320000000)
+		config = GEM_BF(CLK, GEM_CLK_DIV128);
+	else
+		config = GEM_BF(CLK, GEM_CLK_DIV224);
 
 	return config;
 }
-- 
2.33.0
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by patchwork-bot+netdevbpf@kernel.org 3 years ago 
Hello:

This patch was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:

On Thu, 16 Mar 2023 10:03:39 +0000 you wrote:
> Currently macb sets clock divisor for pclk up to 160 MHz.
> Function gem_mdc_clk_div was updated to enable divisor
> for higher values of pclk.
> 
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
> ---
>  drivers/net/ethernet/cadence/macb.h      | 2 ++
>  drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)

Here is the summary with links:
  - net: macb: Set MDIO clock divisor for pclk higher than 160MHz
    https://git.kernel.org/netdev/net-next/c/b31587feaa01

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Andrew Lunn 3 years ago 
On Thu, Mar 16, 2023 at 10:03:39AM +0000, Bartosz Wawrzyniak wrote:
> Currently macb sets clock divisor for pclk up to 160 MHz.
> Function gem_mdc_clk_div was updated to enable divisor
> for higher values of pclk.
> 
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
> ---
>  drivers/net/ethernet/cadence/macb.h      | 2 ++
>  drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..c1fc91c97cee 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -692,6 +692,8 @@
>  #define GEM_CLK_DIV48				3
>  #define GEM_CLK_DIV64				4
>  #define GEM_CLK_DIV96				5
> +#define GEM_CLK_DIV128				6
> +#define GEM_CLK_DIV224				7

Do these divisors exist for all variants? I'm just wondering why these
are being added now, rather than back in 2011-03-09.

   Andrew
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Nicolas Ferre 3 years ago 
Andrew,

On 16/03/2023 at 20:34, Andrew Lunn wrote:
> On Thu, Mar 16, 2023 at 10:03:39AM +0000, Bartosz Wawrzyniak wrote:
>> Currently macb sets clock divisor for pclk up to 160 MHz.
>> Function gem_mdc_clk_div was updated to enable divisor
>> for higher values of pclk.
>>
>> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
>> ---
>>   drivers/net/ethernet/cadence/macb.h      | 2 ++
>>   drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>>   2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
>> index 14dfec4db8f9..c1fc91c97cee 100644
>> --- a/drivers/net/ethernet/cadence/macb.h
>> +++ b/drivers/net/ethernet/cadence/macb.h
>> @@ -692,6 +692,8 @@
>>   #define GEM_CLK_DIV48                                3
>>   #define GEM_CLK_DIV64                                4
>>   #define GEM_CLK_DIV96                                5
>> +#define GEM_CLK_DIV128                               6
>> +#define GEM_CLK_DIV224                               7
> 
> Do these divisors exist for all variants? I'm just wondering why these
> are being added now, rather than back in 2011-03-09.

I see them existing in all variants of "GEM" controller and the older 
"MACB" uses a different path so I think that we are save enabling these 
values.

The values were not added back in the days because the SoC where the 
controller was used didn't reach the frequencies that we are observing 
today for pclk. Divisors weren't needed and field even not completely 
described in Microchip datasheets.

Hope that this sheds some light. Best regards,
   Nicolas

-- 
Nicolas Ferre
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Andrew Lunn 3 years ago 
> I see them existing in all variants of "GEM" controller and the older "MACB"
> uses a different path so I think that we are save enabling these values.

Great. Thanks for checking.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

FYI: Documentation/devicetree/bindings/net/mdio.yaml defines:

  clock-frequency:
    description:
      Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
      defined 2.5MHz should only be used when all devices on the bus support
      the given clock speed.

So you could if you want make the bus speed configurable. Some devices
do work at faster than 2.5MHz, which can be nice if you have a lot of
traffic, e.g. an Ethernet switch, or raw TDR cable test data.

    Andrew
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Nicolas Ferre 3 years ago 
On 16/03/2023 at 11:03, Bartosz Wawrzyniak wrote:
> Currently macb sets clock divisor for pclk up to 160 MHz.
> Function gem_mdc_clk_div was updated to enable divisor
> for higher values of pclk.
> 
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>

Looks good to me:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Thanks for your patch. Best regards,
   Nicolas

> ---
>   drivers/net/ethernet/cadence/macb.h      | 2 ++
>   drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>   2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..c1fc91c97cee 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -692,6 +692,8 @@
>   #define GEM_CLK_DIV48                          3
>   #define GEM_CLK_DIV64                          4
>   #define GEM_CLK_DIV96                          5
> +#define GEM_CLK_DIV128                         6
> +#define GEM_CLK_DIV224                         7
> 
>   /* Constants for MAN register */
>   #define MACB_MAN_C22_SOF                       1
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 6e141a8bbf43..8708af6d25ed 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2641,8 +2641,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
>                  config = GEM_BF(CLK, GEM_CLK_DIV48);
>          else if (pclk_hz <= 160000000)
>                  config = GEM_BF(CLK, GEM_CLK_DIV64);
> -       else
> +       else if (pclk_hz <= 240000000)
>                  config = GEM_BF(CLK, GEM_CLK_DIV96);
> +       else if (pclk_hz <= 320000000)
> +               config = GEM_BF(CLK, GEM_CLK_DIV128);
> +       else
> +               config = GEM_BF(CLK, GEM_CLK_DIV224);
> 
>          return config;
>   }
> --
> 2.33.0
> 

-- 
Nicolas Ferre
Re: [PATCH] net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Posted by Michal Kubiak 3 years ago 
On Thu, Mar 16, 2023 at 10:03:39AM +0000, Bartosz Wawrzyniak wrote:
> Currently macb sets clock divisor for pclk up to 160 MHz.
> Function gem_mdc_clk_div was updated to enable divisor
> for higher values of pclk.
> 
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
> ---
>  drivers/net/ethernet/cadence/macb.h      | 2 ++
>  drivers/net/ethernet/cadence/macb_main.c | 6 +++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 14dfec4db8f9..c1fc91c97cee 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -692,6 +692,8 @@
>  #define GEM_CLK_DIV48				3
>  #define GEM_CLK_DIV64				4
>  #define GEM_CLK_DIV96				5
> +#define GEM_CLK_DIV128				6
> +#define GEM_CLK_DIV224				7
>  
>  /* Constants for MAN register */
>  #define MACB_MAN_C22_SOF			1
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 6e141a8bbf43..8708af6d25ed 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -2641,8 +2641,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
>  		config = GEM_BF(CLK, GEM_CLK_DIV48);
>  	else if (pclk_hz <= 160000000)
>  		config = GEM_BF(CLK, GEM_CLK_DIV64);
> -	else
> +	else if (pclk_hz <= 240000000)
>  		config = GEM_BF(CLK, GEM_CLK_DIV96);
> +	else if (pclk_hz <= 320000000)
> +		config = GEM_BF(CLK, GEM_CLK_DIV128);
> +	else
> +		config = GEM_BF(CLK, GEM_CLK_DIV224);
>  
>  	return config;
>  }

Hi,

The patch looks OK.

Thanks,
Michal

Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>

> -- 
> 2.33.0
>

Patchew 2.1-devel-ea86937

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