[v5] x86: enable FRED for x86-64

[PATCH v5 25/34] x86/fred: disallow the swapgs instruction when FRED is enabled

Posted by Xin Li 2 years, 2 months ago

From: "H. Peter Anvin (Intel)" <hpa@zytor.com>

The FRED architecture establishes the full supervisor/user through:
1) FRED event delivery swaps the value of the GS base address and
   that of the IA32_KERNEL_GS_BASE MSR.
2) ERETU swaps the value of the GS base address and that of the
   IA32_KERNEL_GS_BASE MSR.
Thus, the swapgs instruction is disallowed when FRED is enabled,
otherwise it cauess #UD.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tested-by: Shan Kang <shan.kang@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---
 arch/x86/kernel/process_64.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 57de166dc61c..ff6594dbea4a 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -165,7 +165,8 @@ static noinstr unsigned long __rdgsbase_inactive(void)
 
 	lockdep_assert_irqs_disabled();
 
-	if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (!cpu_feature_enabled(X86_FEATURE_FRED) &&
+	    !cpu_feature_enabled(X86_FEATURE_XENPV)) {
 		native_swapgs();
 		gsbase = rdgsbase();
 		native_swapgs();
@@ -190,7 +191,8 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase)
 {
 	lockdep_assert_irqs_disabled();
 
-	if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
+	if (!cpu_feature_enabled(X86_FEATURE_FRED) &&
+	    !cpu_feature_enabled(X86_FEATURE_XENPV)) {
 		native_swapgs();
 		wrgsbase(gsbase);
 		native_swapgs();
-- 
2.34.1

Re: [PATCH v5 25/34] x86/fred: disallow the swapgs instruction when FRED is enabled

Posted by Peter Zijlstra 2 years, 1 month ago

On Mon, Mar 06, 2023 at 06:39:37PM -0800, Xin Li wrote:
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
> 
> The FRED architecture establishes the full supervisor/user through:
> 1) FRED event delivery swaps the value of the GS base address and
>    that of the IA32_KERNEL_GS_BASE MSR.
> 2) ERETU swaps the value of the GS base address and that of the
>    IA32_KERNEL_GS_BASE MSR.
> Thus, the swapgs instruction is disallowed when FRED is enabled,
> otherwise it cauess #UD.
                 ^^^ --- new word :-)

RE: [PATCH v5 25/34] x86/fred: disallow the swapgs instruction when FRED is enabled

Posted by Li, Xin3 2 years, 1 month ago

> > The FRED architecture establishes the full supervisor/user through:
> > 1) FRED event delivery swaps the value of the GS base address and
> >    that of the IA32_KERNEL_GS_BASE MSR.
> > 2) ERETU swaps the value of the GS base address and that of the
> >    IA32_KERNEL_GS_BASE MSR.
> > Thus, the swapgs instruction is disallowed when FRED is enabled,
> > otherwise it cauess #UD.
>                  ^^^ --- new word :-)

My stupid fingers...