On 10.03.2023 04:14, Sibi Sankar wrote:
> Hey Konrad,
>
> Thanks for the patch.
>
> On 3/4/23 03:28, Konrad Dybcio wrote:
>> Enable the CPUCP block responsible for scaling the L3 cache.
>
> FWIW, the patch just enables the l3 provider, the CPUCP block would
> already be up at this point. You would also want to include the
> expansion for CPUCP at least once in your patch.
Right, I didn't think much about this, but I should probably reword
this and the bindings commit to mention that CPUCP != L3 scaler within.
Konrad
>
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
>
>> ---
>> arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> index 90f18754a63b..59d7ed25aa36 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> @@ -1505,6 +1505,15 @@ frame@f42d000 {
>> };
>> };
>> + cpucp_l3: interconnect@fd90000 {
>> + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
>> + reg = <0 0x0fd90000 0 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>> +
>> cpufreq_hw: cpufreq@fd91000 {
>> compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
>> reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
>>