From: Heiko Stuebner <heiko.stuebner@vrull.eu>
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
arch/riscv/include/asm/csr.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index add51662b7c3..8b06f2472915 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -176,6 +176,11 @@
#define ENVCFG_CBIE_INV _AC(0x3, UL)
#define ENVCFG_FIOM _AC(0x1, UL)
+/* VCSR flags */
+#define VCSR_VXRM_MASK 3
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXSAT_MASK 1
+
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
--
2.39.0
On Tue, Feb 28, 2023 at 10:54:34PM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > Define constants for those to access the elements in a readable way. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/csr.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index add51662b7c3..8b06f2472915 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -176,6 +176,11 @@ > #define ENVCFG_CBIE_INV _AC(0x3, UL) > #define ENVCFG_FIOM _AC(0x1, UL) > > +/* VCSR flags */ > +#define VCSR_VXRM_MASK 3 > +#define VCSR_VXRM_SHIFT 1 > +#define VCSR_VXSAT_MASK 1 > + > /* symbolic CSR names: */ > #define CSR_CYCLE 0xc00 > #define CSR_TIME 0xc01 > -- > 2.39.0 >
Acked-by: Guo Ren <guoren@kernel.org> On Wed, Mar 1, 2023 at 5:54 AM Heiko Stuebner <heiko@sntech.de> wrote: > > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > Define constants for those to access the elements in a readable way. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > --- > arch/riscv/include/asm/csr.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index add51662b7c3..8b06f2472915 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -176,6 +176,11 @@ > #define ENVCFG_CBIE_INV _AC(0x3, UL) > #define ENVCFG_FIOM _AC(0x1, UL) > > +/* VCSR flags */ > +#define VCSR_VXRM_MASK 3 > +#define VCSR_VXRM_SHIFT 1 > +#define VCSR_VXSAT_MASK 1 > + > /* symbolic CSR names: */ > #define CSR_CYCLE 0xc00 > #define CSR_TIME 0xc01 > -- > 2.39.0 > -- Best Regards Guo Ren
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