Starfive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/phy/starfive,jh7110-dphy-rx.yaml | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
new file mode 100644
index 000000000000..a67ca57a6f21
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SoC MIPI D-PHY Rx Controller
+
+maintainers:
+ - Jack Zhu <jack.zhu@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The Starfive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer
+ CSI camera data.
+
+properties:
+ compatible:
+ const: starfive,jh7110-dphy-rx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: cfg
+ - const: ref
+ - const: tx
+
+ resets:
+ items:
+ - description: DPHY_HW reset
+ - description: DPHY_B09_ALWAYS_ON reset
+
+ starfive,aon-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of AON SYSCON
+ - description: register offset
+ description: The power of dphy rx is configured by AON SYSCON
+ in this property.
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - starfive,aon-syscon
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@19820000 {
+ compatible = "starfive,jh7110-dphy-rx";
+ reg = <0x19820000 0x10000>;
+ clocks = <&ispcrg 3>,
+ <&ispcrg 4>,
+ <&ispcrg 5>;
+ clock-names = "cfg", "ref", "tx";
+ resets = <&ispcrg 2>,
+ <&ispcrg 3>;
+ starfive,aon-syscon = <&aon_syscon 0x00>;
+ #phy-cells = <0>;
+ };
--
2.25.1On Wed, Feb 22, 2023 at 05:59:50PM -0800, Changhuang Liang wrote:
> Starfive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
> a M31 IP. Add a binding for it.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 74 +++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
> new file mode 100644
> index 000000000000..a67ca57a6f21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Starfive SoC MIPI D-PHY Rx Controller
> +
> +maintainers:
> + - Jack Zhu <jack.zhu@starfivetech.com>
> + - Changhuang Liang <changhuang.liang@starfivetech.com>
> +
> +description:
> + The Starfive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer
> + CSI camera data.
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-dphy-rx
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: cfg
> + - const: ref
> + - const: tx
Should be 'rx' given this is the 'rx' block? A description of each clock
in 'clocks' would be good.
> +
> + resets:
> + items:
> + - description: DPHY_HW reset
> + - description: DPHY_B09_ALWAYS_ON reset
> +
> + starfive,aon-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
- items: ?
Otherwise, multiple 2 cell entries are allowed. Is that intended?
> + - description: phandle of AON SYSCON
> + - description: register offset
> + description: The power of dphy rx is configured by AON SYSCON
> + in this property.
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - starfive,aon-syscon
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy@19820000 {
> + compatible = "starfive,jh7110-dphy-rx";
> + reg = <0x19820000 0x10000>;
> + clocks = <&ispcrg 3>,
> + <&ispcrg 4>,
> + <&ispcrg 5>;
> + clock-names = "cfg", "ref", "tx";
> + resets = <&ispcrg 2>,
> + <&ispcrg 3>;
> + starfive,aon-syscon = <&aon_syscon 0x00>;
> + #phy-cells = <0>;
> + };
> --
> 2.25.1
>
On 2023/2/28 2:34, Rob Herring wrote: > On Wed, Feb 22, 2023 at 05:59:50PM -0800, Changhuang Liang wrote: [...] >> + >> + clocks: >> + maxItems: 3 >> + >> + clock-names: >> + items: >> + - const: cfg >> + - const: ref >> + - const: tx > > Should be 'rx' given this is the 'rx' block? A description of each clock > in 'clocks' would be good. > 'tx': This clock is directly used to generate transmit escape sequences, will add description of each clock in 'clocks'. >> + >> + resets: >> + items: >> + - description: DPHY_HW reset >> + - description: DPHY_B09_ALWAYS_ON reset >> + >> + starfive,aon-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + items: > > - items: ? > > Otherwise, multiple 2 cell entries are allowed. Is that intended? > Will change to: items: - items: >> + - description: phandle of AON SYSCON >> + - description: register offset >> + description: The power of dphy rx is configured by AON SYSCON >> + in this property. > > >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - reg [...] >> -- >> 2.25.1 >>
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