Add the compatible and configuration values
for A73 Huayra PLL found on IPQ9574
Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Rebased the changes on the below series which refactors the
driver to accommodate Huayra & Stromer Plus PLLs
https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
- Changed the hex value in ipq9574_pll_config to lowercase
- Dropped the mailbox driver changes as ipq9574 mailbox is
compatible with ipq6018
drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index cf4f0d340cbf..ce28d882ee78 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
.test_ctl_hi_val = 0x4000,
};
+static const struct alpha_pll_config ipq9574_pll_config = {
+ .l = 0x3b,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x6,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x4000,
+};
+
struct apss_pll_data {
int pll_type;
struct clk_alpha_pll *pll;
@@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
.pll_config = &ipq6018_pll_config,
};
+static struct apss_pll_data ipq9574_pll_data = {
+ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
+ .pll = &ipq_pll_huayra,
+ .pll_config = &ipq9574_pll_config,
+};
+
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
+ { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
--
2.17.1
On 17.02.2023 14:41, Devi Priya wrote:
The subject is.. weird.. something like:
clk: qcom: apss-ipq-pll: add support for IPQ9574
would have made more sense, as you're not enabling the clock
driver, and certainly not *in* the SoC.
> Add the compatible and configuration values
Generally the lines in commit messages should be broken at 70-75
chars, not 40.
> for A73 Huayra PLL found on IPQ9574
>
> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Is Praveenkumar's last name "I"?
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
Otherwise the code looks good, I think.
Konrad
> Changes in V2:
> - Rebased the changes on the below series which refactors the
> driver to accommodate Huayra & Stromer Plus PLLs
> https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
> - Changed the hex value in ipq9574_pll_config to lowercase
> - Dropped the mailbox driver changes as ipq9574 mailbox is
> compatible with ipq6018
>
> drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index cf4f0d340cbf..ce28d882ee78 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
> .test_ctl_hi_val = 0x4000,
> };
>
> +static const struct alpha_pll_config ipq9574_pll_config = {
> + .l = 0x3b,
> + .config_ctl_val = 0x200d4828,
> + .config_ctl_hi_val = 0x6,
> + .early_output_mask = BIT(3),
> + .aux2_output_mask = BIT(2),
> + .aux_output_mask = BIT(1),
> + .main_output_mask = BIT(0),
> + .test_ctl_val = 0x0,
> + .test_ctl_hi_val = 0x4000,
> +};
> +
> struct apss_pll_data {
> int pll_type;
> struct clk_alpha_pll *pll;
> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
> .pll_config = &ipq6018_pll_config,
> };
>
> +static struct apss_pll_data ipq9574_pll_data = {
> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
> + .pll = &ipq_pll_huayra,
> + .pll_config = &ipq9574_pll_config,
> +};
> +
> static const struct regmap_config ipq_pll_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
> { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
> + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
> { }
> };
> MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
On 2/17/2023 7:43 PM, Konrad Dybcio wrote:
>
>
> On 17.02.2023 14:41, Devi Priya wrote:
> The subject is.. weird.. something like:
>
> clk: qcom: apss-ipq-pll: add support for IPQ9574
>
> would have made more sense, as you're not enabling the clock
> driver, and certainly not *in* the SoC.
Yes agreed. Will update this in V3
>
>> Add the compatible and configuration values
> Generally the lines in commit messages should be broken at 70-75
> chars, not 40.
>
Okay
>> for A73 Huayra PLL found on IPQ9574
>>
>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Is Praveenkumar's last name "I"?
yes, it is
>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
> Otherwise the code looks good, I think.
Sure, thanks
>
> Konrad
>> Changes in V2:
>> - Rebased the changes on the below series which refactors the
>> driver to accommodate Huayra & Stromer Plus PLLs
>> https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
>> - Changed the hex value in ipq9574_pll_config to lowercase
>> - Dropped the mailbox driver changes as ipq9574 mailbox is
>> compatible with ipq6018
>>
>> drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
>> index cf4f0d340cbf..ce28d882ee78 100644
>> --- a/drivers/clk/qcom/apss-ipq-pll.c
>> +++ b/drivers/clk/qcom/apss-ipq-pll.c
>> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
>> .test_ctl_hi_val = 0x4000,
>> };
>>
>> +static const struct alpha_pll_config ipq9574_pll_config = {
>> + .l = 0x3b,
>> + .config_ctl_val = 0x200d4828,
>> + .config_ctl_hi_val = 0x6,
>> + .early_output_mask = BIT(3),
>> + .aux2_output_mask = BIT(2),
>> + .aux_output_mask = BIT(1),
>> + .main_output_mask = BIT(0),
>> + .test_ctl_val = 0x0,
>> + .test_ctl_hi_val = 0x4000,
>> +};
>> +
>> struct apss_pll_data {
>> int pll_type;
>> struct clk_alpha_pll *pll;
>> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
>> .pll_config = &ipq6018_pll_config,
>> };
>>
>> +static struct apss_pll_data ipq9574_pll_data = {
>> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
>> + .pll = &ipq_pll_huayra,
>> + .pll_config = &ipq9574_pll_config,
>> +};
>> +
>> static const struct regmap_config ipq_pll_regmap_config = {
>> .reg_bits = 32,
>> .reg_stride = 4,
>> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
>> { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
>> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
>> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
>> + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
>> { }
>> };
>> MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
Best Regards,
Devi Priya
© 2016 - 2025 Red Hat, Inc.