Enable Crashdump collection in ipq9574
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
---
Changes in V3:
- No changes
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2b86ba17bb32..9c4523f50a57 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -81,6 +81,13 @@
reg = <0x0 0x40000000 0x0 0x0>;
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq9574", "qcom,scm";
+ qcom,dload-mode = <&tcsr_boot_misc 0>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a73-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -95,11 +102,17 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
-
tz_region: tz@4a600000 {
reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
};
+
+ smem@4aa00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ hwlocks = <&tcsr_mutex 0>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -150,6 +163,17 @@
#power-domain-cells = <1>;
};
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01905000 0x8000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr_boot_misc: syscon@193d100 {
+ ompatible = "qcom,tcsr-ipq9574", "syscon";
+ reg = <0x0193d100 0x4>;
+ };
+
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
--
2.17.1
On 08/02/2023 06:33, Poovendhan Selvaraj wrote:
> Enable Crashdump collection in ipq9574
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> ---
> Changes in V3:
> - No changes
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2b86ba17bb32..9c4523f50a57 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -81,6 +81,13 @@
> reg = <0x0 0x40000000 0x0 0x0>;
> };
>
> + firmware {
> + scm {
> + compatible = "qcom,scm-ipq9574", "qcom,scm";
> + qcom,dload-mode = <&tcsr_boot_misc 0>;
> + };
> + };
> +
> pmu {
> compatible = "arm,cortex-a73-pmu";
> interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> @@ -95,11 +102,17 @@
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> -
I don't think anything improved here - still unrelated change.
Best regards,
Krzysztof
On 2/8/2023 1:29 PM, Krzysztof Kozlowski wrote:
> On 08/02/2023 06:33, Poovendhan Selvaraj wrote:
>> Enable Crashdump collection in ipq9574
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
>> ---
>> Changes in V3:
>> - No changes
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++-
>> 1 file changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 2b86ba17bb32..9c4523f50a57 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -81,6 +81,13 @@
>> reg = <0x0 0x40000000 0x0 0x0>;
>> };
>>
>> + firmware {
>> + scm {
>> + compatible = "qcom,scm-ipq9574", "qcom,scm";
>> + qcom,dload-mode = <&tcsr_boot_misc 0>;
>> + };
>> + };
>> +
>> pmu {
>> compatible = "arm,cortex-a73-pmu";
>> interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> @@ -95,11 +102,17 @@
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> -
> I don't think anything improved here - still unrelated change.
>
>
> Best regards,
> Krzysztof
Okay sure...next series will add required smem and download mode nodes
in different patches.
Regards,
Poovendhan S
On 14/02/2023 05:11, POOVENDHAN SELVARAJ wrote:
>
> On 2/8/2023 1:29 PM, Krzysztof Kozlowski wrote:
>> On 08/02/2023 06:33, Poovendhan Selvaraj wrote:
>>> Enable Crashdump collection in ipq9574
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
>>> ---
>>> Changes in V3:
>>> - No changes
>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++-
>>> 1 file changed, 25 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> index 2b86ba17bb32..9c4523f50a57 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -81,6 +81,13 @@
>>> reg = <0x0 0x40000000 0x0 0x0>;
>>> };
>>>
>>> + firmware {
>>> + scm {
>>> + compatible = "qcom,scm-ipq9574", "qcom,scm";
>>> + qcom,dload-mode = <&tcsr_boot_misc 0>;
>>> + };
>>> + };
>>> +
>>> pmu {
>>> compatible = "arm,cortex-a73-pmu";
>>> interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> @@ -95,11 +102,17 @@
>>> #address-cells = <2>;
>>> #size-cells = <2>;
>>> ranges;
>>> -
>> I don't think anything improved here - still unrelated change.
>>
>>
>> Best regards,
>> Krzysztof
>
> Okay sure...next series will add required smem and download mode nodes
> in different patches.
I commented the diff - specific hunk - which is unrelated.
Best regards,
Krzysztof
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